一个异步低功耗微控制器的结构设计与VLSI实现

介绍了一个低功耗微控制器的结构设计与VLSI电路实现。适当地选择并设计了微控制器的体系结构和流水线,同时采用了异步逻辑的电路实现方法。该微控制器与PIC16C61的指令集兼容,功能相仿。在Chartered0.6μm 的工艺条件下,平均功耗只有PIC16C61的16％。与其它各种类型的现有微控制器相比,功耗的下降更为明显。     

一种GF(2~k)域的高效乘法器及其VLSI实现

在分析全串行和全并行 GF(2 k)域乘法的基本原理基础上提出了一种适合于任意 GF(2 k)域的乘法器 UHGM(U nified Hybrid Galois Field Multiplier) .它为当前特别重要的 k为素数的 GF(2 k)域乘法 ,提供了一种高效的实现方法 .该乘法器具有结构规整、模块化好的特点 ,特别适合于 VL SI实现 ,同时这种结构具有粗粒度的面积和速度的可伸缩性 ,方便了在大范围内进行实现面积和速度的权衡 .最后给出了 GF(2 1 6 3)域上乘法器的 ASIC综合的结果     

JPEG2000实时截断码率控制新算法及其VLSI结构设计

提出一种实时编码实时截断的码率控制算法.它根据已分解的小波子带内码块有效位平面数来预测未分解的小波子带内码块有效位平面数,并根据编码通道数和小波/量化权系数为当前编码码块分配码率.并提出一种JPEG2000编码实时截断,两级码率控制的编码体系结构.第一级采用本文提出的算法实时截断码流和编码通道.第二级在低码率下采用JPEG2000标准的PCRD优化算法搜索精确的分层截断点.在最优分层截断之前多数码流和编码通道被预先截断,存储器损耗小,实时性高.低码率下,图像质量跟JPEG2000标准一致.     

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human–computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.     

A bit-level systolic array for digital contour smoothing

Linear operators for digital contour smoothing are described. These operators are defined by circulant Toeplitz matrices and allow to smooth digital contours in the least-squares sense. They minimize the undersampling, digitizing and quantizing error and allow to calculate invariants, such as curvature, which are not possible to calculate without smoothing. A bit-level systolic array which is capable of realizing the proposed operator is described. This array is easy to implement in VLSI, because the array cells involved are very simple. Furthermore, the array is completely pipelined on the bit-level, so that it operates with a high clock frequency achieving very high throughputs.     

A design of time-optimum and register-number-minimum systolic convolvers

We present an optimum bit-parallel/word-sequential systolic convolver. Our design is the best one among the previous many convolvers in the sense that its optimality in time and space performances is simultaneously attained without augmenting any global control, broadcasting, initial-data-preloading, and/or multi-sequential or parallel I/O ports which were allowed in most of the previous designs. As an application of our convolver we give a systolic polynomial divider which can compute the polynomial division in exactly n + O(1) optimum steps on [min(n−m, m)/2]+O(1) systolic cells for the division of any degree n polynomial by any degree m polynomial (n m).     

VLSI systems for band matrix multiplication

We examine several VLSI architectures and compare these for their suitability for various forms of the band matrix multiplication problem. The following architectures are considered: chain, broadcast chain, mesh, broadcast mesh and hexagonally connected. The forms of the matrix multiplication problem that are considered are: band matrix × vector and band matrix × band matrix. Metrics to measure the utilization of resources (bandwidth and processors) are also proposed. An important feature of this paper is the inclusion of correctness proofs. These proofs are provided for selected designs and illustrate how VLSI designs may be proved correct using traditional mathematical tools.     

Shape detection with limited memory

A new approach to shape detection through the generalized Hough transform is introduced. The method is based on a limited memory implementation of the transform, that reduces its cost and makes it suitable for hardware implementation. The rationale of the method is that a shape is bound by a circle whose radius is, in most practical situations, much smaller than the dimensions of the image processed. This a priori knowledge can be used during the vote collection phase of the transform to guide flushing operations against a filled memory. The method is tested in the simple case of circles detection and in more practical situations of IC inspection.     

An algorithm ofk-line location for BBL in LSI/VLSI

In this paper, aK-line location algorithm for building block cells in LSI/VLSI is presented. When the relative positions of rectangular cells are given, there are 2 states according to the two orientations of a cell. It is proved that to find the optimum solution from the 2^N states can be reduced to calculate theN states inK-line algorithm. So the algorithm is shown very effective and can be used with association for cluster method in BBL placement. Under certain conditions, this method can also be used to pesudo BBL placement directly.     

应用于VLSI的PSSWS-LDD MOSFET优化工艺研究

提出实现VLSI的PSSWS(Poly Silicon Side Wall Spacer)—LDD(Lightly DopedDrain)结构,研究了它的形成工艺,获得多晶侧壁形成的优化工艺条件,制作出亚微米有效沟道长度的LDD NMOSFET。在器件性能研究和计算机模拟的基础上,得到PSSWS—LDDMOSFET的优化工艺实现条件;此条件下实现的有效沟道长为0.8μm的PSSWS—LDDNMOSFET,源漏击穿电压达20V,常规器件的小于16V;衬底电流较常规器件的减小约二个数量级。利用此优化条件,研制出高性能的1μm沟道长度的CMOS CD4007电路,2μm沟道长的21级CMOS环振,LSI CMOS 2.5μm沟道长度的门阵列电路GA 300 5SD。结果表明:PSSWS—LDD MOSFET性能衰退小,速度快,可靠性高,适用于VLSI的制造。