基于分治策略的加法器测试向量生成技术

为应对数据通道测试中向量生成计算复杂度的日益增长,针对加法器进行研究,提出了一种基于分治策略的加法器测试向量生成技术。首先将被测加法器电路分解为并发模块和顺序模块,分别生成对应这些模块故障全覆盖的测试向量子集,再将他们的输入信号映射为被测加法器电路的基本输入,经去除冗余向量后得到完整的测试向量集。给出的实验结果表明了该技术能有效地降低加法器测试向量生成的计算量,特别对于大规模加法器电路的测试生成,其效果更佳。     

专用超大规模集成电路在LED显示系统中的应用

自1976年蒙特利尔奥运会采用了第一块黑白视频显示屏以来，各种大屏幕特别是LED显示屏得到了迅猛发展，在现代信息社会中更是随处可见。在这些显示系统中，应用了大量的不同种类的集成电路作为驱动芯片。本文叙述了运用于LED显示系统中的超大规模集成电路的强大功能。     

DES加密算法的VLSI实现方法

简述了DES加密算法的发展历史和核心思想,并给出了一种VLSI实现方法.并且在数据通道中采用了流水线结构,这样的结构比软件实现有着更好的加密性能.文中着重介绍了DES算法中的S-Box,替换和迭代过程.     

一种高性能的适用于AVS的二维整数逆变换实现结构

针对AVS视频标准中的整数逆变换,本文提出了一种高性能的硬件实现方案.本方案采用两个一维逆变换核和4个16(16的双口SRAM.通过合理控制SRAM的读写方式,避免了数据的预处理与后处理,流水线的深度也得到减少.在列变换时,改变数据运算次序,从而保证了4个双口SRAM不影响运算速度.处理8(8的数据块,本结构仅需要37个时钟,与传统的实现方案相比,在同等运算速度下,面积节约28%.实验表明该结构适用于采用AVS标准的HDTV编解码器.     

A reconfigurable VLSI-based double-lens tracking camera

Watching and tracking an object while seeing a much wider view is one of advantages of the eye system. We proposed and developed a tracking camera system that mimics the eyes by using double-lens modules. In the system, a wide view is captured through the wide-lens module, while the target in it is tracked and magnified through the telescopic lens module. Electronic circuits for tracking control are implemented onto the reconfigurable VLSI or FPGA in order to embed the parallelism in the tracking algorithm into the hardware. A successfully developed FPGA-based prototype performs high-speed tracking at the video-rate. This work was present in part at the 12th International Symposium on Artificial Life and Robotics, Oita, Japan, January 25–27, 2007     

Optimal algorithms for adjacent side routing

We consider the switchbox routing problem of two-terminal nets in the case when all thek nets lie on two adjacent sides of the rectangle. Our routing model is the standard two-layer model. We develop an optimal algorithm that routes all the nets whenever a routing exists. The routing obtained uses the fewest possible number of vias. A more general version of this problem (adjacent staircase) is also optimally solved.This research was supported in part by NSA Contract No. MDA-904-85H-0015, NSF Grant No. DCR-86-00378, and by NSF Engineering Research Centers Program NSFD CDR 88003012.     

适用于VLSI设计的LVV数据模型及其数据库管理系统

本文分析了VLSI设计中的数据类型和相互关系,提出了适用于VLSI设计的LVV数据模型,它包含对象、版本、视图和文档四个基本概念,支持面向对象的数据操作,描述设计对象的层次结构和设计衍变过程,且根据模型的语义性可进行数据完整性及描述等价性的控制.LVV系统是建立在LVV模型基础上的数据库管理系统,除上述数据模型所提供的特点外,还具有统一的用户界面和数据共享性好等特点.     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

A greedy switch-box router

The greedy channel router of Rivest and Fiduccia is extended into an efficient switch-box router. The algorithm is based on two simple operations called join-split-nets and jog-to-right-target derived from the channel router. Terminals are on the boundary of a rectangular region, and the router uses two orthogonal layers of wires to generate the solution. The router always succeeds in finding a solution by inserting sufficient horizontal and vertical tracks in case of insufficient routing area. The result is generated through a single column-wise scan across the routing region. The expected running time is proportional to M(N + N_net), where M, N and N_net are respectively the number of columns, rows and nets in the region. The scan direction is crucial to the algorithm and we have proposed good heuristic which is based on the augmented channel density distribution in finding it. Results from a number of examples are evaluated. The implemented router is designed for assembling custom VLSI designs, it works in parallel with other tools such as a layout editor via a simple interface. The router output is in CIF.     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.