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71.
Yuan Baoguo 《电子科学学刊(英文版)》2005,(4)
The Balanced Truncation Method (BTM) is applied to an even distributed RC interconnect case by using Wang's closed-forms of even distributed RC interconnect models. The results show that extremely high order RC interconnect can be high-accurately approximated by only third order balanced model. Related simulations are executed in both time domain and frequency domain. The results may be applied to VLSI interconnect model reduction and design. 相似文献
72.
Xiong Chengyi Tian Jinwen Liu Jian Gao Zhirong 《电子科学学刊(英文版)》2006,23(2):244-248
A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area. 相似文献
73.
In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented. 相似文献
74.
连续小波变换VLSI实现综述 总被引:13,自引:2,他引:11
小波变换是信号处理、图像压缩和模式识别等诸多领域中一个非常有效的数学分析工具。然而,实时小波变换计算量大,需要专用硬件来实现。连续小波变换的VLSI实现在处理速度、功耗及适用频率范围方面部具有较明显的优势,且实现方法灵活。本文对近年来有关该领域的研究情况作了综合评述,讨论了其中存在的问题,并指出了今后的若干发展方向,特别是瞬时缩展电路技术是实现低电压低功耗小波变换芯片的重要途经之一。 相似文献
75.
76.
简述了DES加密算法的发展历史和核心思想,并给出了一种VLSI实现方法.并且在数据通道中采用了流水线结构,这样的结构比软件实现有着更好的加密性能.文中着重介绍了DES算法中的S-Box,替换和迭代过程. 相似文献
77.
一种高性能的适用于AVS的二维整数逆变换实现结构 总被引:1,自引:0,他引:1
针对AVS视频标准中的整数逆变换,本文提出了一种高性能的硬件实现方案.本方案采用两个一维逆变换核和4个16(16的双口SRAM.通过合理控制SRAM的读写方式,避免了数据的预处理与后处理,流水线的深度也得到减少.在列变换时,改变数据运算次序,从而保证了4个双口SRAM不影响运算速度.处理8(8的数据块,本结构仅需要37个时钟,与传统的实现方案相比,在同等运算速度下,面积节约28%.实验表明该结构适用于采用AVS标准的HDTV编解码器. 相似文献
78.
79.
Moritoshi Yasunaga Jung Hwan Kim Ikuo Yoshihara 《Genetic Programming and Evolvable Machines》2001,2(3):211-230
In this paper, we propose evolvable reasoning hardware and its design methodology. In the proposed design methodology, case databases of each reasoning task are transformed into truth tables, which are evolved to extract rules behind the past cases through a genetic algorithm. Circuits for the evolvable reasoning hardware are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits through the direct hardware implementation of the case databases. We developed the evolvable reasoning hardware prototype using Xilinx Virtex FPGA chips and applied it to the English-pronunciation-reasoning (EPR) task. The evolvable reasoning hardware for the EPR task was implemented with 270K gates, achieving an extremely high reasoning speed of less than 300 ns/phoneme. It also achieved a reasoning accuracy of 82.1% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI. 相似文献
80.
Saeid Mos lehpour Srikrishna Karatalapu 《通讯和计算机》2009,6(10):44-53
The Arithmetic and Logic Unit (ALU) is a combination circuit that performs a number of arithmetic and logical operations within a microprocessor. The demand for faster and compact ALUs makes it desirable to test the ALU in conjunction with pre-design parts prior to manufacture. This may be accomplished in a process using CAD and SPICE simulation software. Our purpose is to realize a method for importing a layout drawn in Tanner L-edit and simulated in T-Spice into PSpice which is referred to as software talking. To do so we use an eight-function instruction set called Complimentary Metal Oxide Semiconductor Arithmetic and Logic Unit (CMOS ALU) which is laid out in Tanner L-edit and produces an extracted net-list which is simulated in T-Spice. An ALU equivalent design is then modeled in PSpice for further testing with pre-manufactured parts of the PSpice library. 相似文献