VLSI电路低功耗设计研究进展

介绍了低功耗设计最新的研究进展,从低功耗设计流程、功耗估计方法、功耗优化方法、功耗优化工具软件、低功耗测试等几个方面,对低功耗的研究进行了系统和科学的阐述,可为相关研究设计人员提供有益的参考.     

Fast‐squarer circuits using 3‐bit‐scan without overlapping bits

This paper presents a novel technique to design fast‐squaring circuits. The proposed approach speeds up squaring operations combining the 3‐bit scan without overlapping bits and the folding technique. Several hardware implementations of squarer circuits designed as described here are characterized for several operand wordlengths. Obtained results demonstrate that, using the ST 90 nm 1V CMOS technology, a 32‐bit squarer exploiting the novel way of generating partial products reaches a 769 MHz running frequency, dissipates less than 19.3 mW on average and occupies ～91 000µm² of silicon area. Copyright © 2010 John Wiley & Sons, Ltd.     

A multi coding technique to reduce transition activity in VLSI circuits

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.     

Statistical timing and power analysis of VLSI considering non-linear dependence

Majority of practical multivariate statistical analysis and optimizations model interdependence among random variables in terms of the linear correlation. Though linear correlation is simple to use and evaluate, in several cases non-linear dependence between random variables may be too strong to ignore. In this paper, we propose polynomial correlation coefficients as simple measure of multi-variable non-linear dependence and show that the need for modeling non-linear dependence strongly depends on the end function that is to be evaluated from the random variables. Then, we calculate the errors in estimation resulting from assuming independence of components generated by linear de-correlation techniques, such as PCA and ICA. The experimental results show that the error predicted by our method is within 1% error compared to the real simulation of statistical timing and leakage analysis. In order to deal with non-linear dependence, we further develop a target-function-driven component analysis algorithm (FCA) to minimize the error caused by ignoring high order dependence. We apply FCA to statistical leakage power analysis and SRAM cell noise margin variation analysis. Experimental results show that the proposed FCA method is more accurate compared to the traditional PCA or ICA.     

FPGA and ASIC implementation of robust invisible binary image watermarking algorithm using connectivity preserving criteria

Digital watermarking is the process of hiding information into a digital signal to authenticate the contents of digital data. There are number of watermarking algorithm implemented in software and few in hardware. This paper discusses the implementation of robust invisible binary image watermarking algorithm in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC) using connectivity preserving criteria. The algorithm is processed in spatial domain. The algorithm is prototyped in (i) XILINX FPGA (ii) 130 nm ASIC. The algorithm is tested in Virtex-E (xcv50e-8-cs144) FPGA and implemented in an ASIC.     

A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

We consider the problem of one-dimensional topological compaction with jog insertions. By combining both geometric and graph-theoretic approaches we present a faster and simpler algorithm to improve over previous results. The compaction algorithm takes as input a sketch consisting of a set F of features and a set W of wires, and minimizes the horizontal width of the sketch while maintaining its routability. The algorithm consists of the following steps: constructing a horizontal constraint graph, computing all possible jog positions, computing the critical path, relocating the features, and reconstructing a new sketch homotopic to the input sketch, which is suitable for detailed routing. The algorithm runs in O(|F| ⋅ |W|) worst-case time and space, which is asymptotically optimal in the worst case. Experimental results are also presented. Received May 16, 1997; revised January 11, 1999.     

Evaluating the quality of project planning: a model and field results

Faulty planning will result in project failure, whereas high-quality project planning increases the project's chances of success. The paper reports on the successful development and implementation of a model aimed at evaluating the quality of project planning. The model is based on both the abilities required of the project manager and the organizational support required for a proper project management infrastructure. The model was validated and applied by 282 project managers in nine organizations, where strong and weak planning processes were identified and analysed.     

High-level parameterizable area estimation modeling for ASIC designs

Architectural design space exploration and early area budgeting for ASIC and IP block development require accurate high level gate count estimation methods without requiring the hardware being fully specified. The proposed method uses hierarchical and parameterizable models requiring minimal amount of information about the implementation technology to meet this goal. The modeling process flow is to: (1) create a block diagram of the design, (2) create a model for each block, and (3) sum up estimates of all sub-blocks by supplying the correct parameters to each sub-model. We discuss the model creation for a few parameterized library blocks as well as three communication blocks and a processor core from real IC projects ranging from 22 to 250 kgates. The average relative estimation error of the proposed method for the library blocks is 3.2% and for the real world examples 4.0%. The best application of this method is early in the design phase when different implementation architectures are compared.     

用于混合信号系统的模/数分块一体化测试技术

为了解决混合信号系统中三种模块:模拟、数字和存储器接口之间存在的难以测试的问题,讨论了一种模拟/数字一体化的测试技术,包括三种模块的测试方法、系统测试的分块、可测性设计(DFT)、自测试策略和方案等,并说明了互连测试和准静态电流IDDQ测试法可为该项新技术提供有效的解决方案.