辐射固化的国际现状——第一届亚洲地区国际辐射固化会议简介

辐射固化技术是辐射加工技术的分支,八十年代以来发展迅速,年增长率在10％以上。用辐射固化的产品种类很多,而磁性介质,隔离涂层,陶瓦瓷砖的装饰面,石膏板装饰表层、印刷板、光纤保护层,电子技术、蚀刻技术、压敏粘合剂等等。实现辐射固化首先要考虑好有关的化学问题。为发展辐射固化技术也应介绍UV/EB固化的安全操作、工业操作规程及专利法等,有关该领域的设备及工业获得很大的进展。     

Wang laboratories' VLSI design strategy or Putting blinders on your engineers keeps your horse in the race

The article discusses the rationale used to make the decision to implement a constrained design capability for VLSI in Wang. A CAD/CAM system will be put in place that will permit product designers to achieve design and manufacturing turn-a-round times that are consistent with a product development cycle of 18 to 24 months. The functional requirements of the various subsystems are discussed as well as those for the excutive, the data base, and the audit capability. The latter capabilities are necessary to achieve a controlled constrained design environment.     

Two-level pipelined systolic array for multidimensional convolution

This paper describes a systolic array for the computation of n-dimensional (nD) convolutions for any positive integer n. Systolic systems usually achieve high performance by allowing computations to be pipelined over a large array of processing elements. To achieve even higher performance, the systolic array described in this paper uses a second level of pipelining by allowing the processing elements themselves to be pipelined to an arbitrary degree.     

Analog VLSI Circuits for Competitive Learning Networks

An investigation is made concerning implementations of competitive learning algorithms in analog VLSI circuits and systems. Analog and low power digital circuits for competitive learning are currently important for their applications in computationally-efficient speech and image compression by vector quantization, as required for example in portable multi-media terminals. A summary of competitive learning models is presented to indicate the type of VLSI computations required, and the effects of weight quantization are discussed. Analog circuit representations of computational primitives for learning and evaluation of distortion metrics are discussed. The present state of VLSI implementations of hard and soft competitive learning algorithms are described, as well as those for topological feature maps. Tolerance of learning algorithms to observed analog circuit properties is reported. New results are also presented from simulations of frequency-sensitive and soft competitive learning concerning sensitivity of these algorithms to precision in VLSI learning computations. Applications of these learning algorithms to unsupervised feature extraction and to vector quantization of speech and images are also described.     

A Vlsi Neural Network Processor Based on Hippocampal Model

The hippocampal region of the brain system can be analyzed with the nonlinear system modeling approach. The input-output relationship of the neural units is best represented by the kernel functions of different complexities. The modeling expression of the first and second order kernels are computed in analog current-mode instead of digital data processing in order to fully explore massively parallel processing capability of the neural networks. Two distinct methods are utilized: the table-look-up approach and the model-based approach. The former can achieve high accuracy but consumes large silicon area while the latter saves silicon area and maintains moderately high accuracy. Circuit-level simulation results and experimental data from two test structures are presented.     

基于边界元法的二维VLSI版图电容提取

提出了一种用边界元法计算ＶＬＳＩ版图电容的方法，通过求解二维拉普拉斯方程，直接得到版图中各种类型的电容的值。该方法提取数据准确简单，占用内存少，计算效率高，且有较高的精度。用该方法对几种典型的ＶＬＳＩ版图电容进行提取，均取得较好的结果。     

基于CORDIC算法并行FFT设计与硬件实现

讨论了复杂128点FFT处理器的并行和旋转结构。VLSI实现FFT适用于超高速数据处理。随着新的VLSI技术的发展，高速处理和低功耗设计成为现实。使用CORDIC旋转处理器可以优化面积和速度的设计，在不降低数据处理速度的基础上，这种FFT仅仅使用了5．3万等效逻辑门。     

行为级DSP算法描述的阵列处理器综合方法研究

本文提出了针对递归DSP算法的高层次系统综合流程,并以脉动(systolic)式处理器阵列结构实现.从DSP算法的FDDL行为级描述开始,经由编译及划分,产生数据相关流图(Data Dependency Graph),然后实现对算法流图的空间映射及时域规划,得到算法的信号流图(Signal Flow Graph),经时序重构,生成脉动阵列,最后实现对处理器单元的数据路径综合及控制器综合,并对处理器单元定位,本文同时提出了各设计阶段的算法策略及优化策略,并给出综合结果。     

神经网络的VLSI实现

本文评述了当前神经网络电路实现的关键技术和研究现状,着重讨论了数字、模拟和脉冲流VLSI实现的电路技术及其未来发展。     

Maximumk-covering of weighted transitive graphs with applications

Consider a weighted transitive graph, where each vertex is assigned a positive weight. Given a positive integerk, the maximumk-covering problem is to findk disjoint cliques covering a set of vertices with maximum total weight. An 0(kn ²)-time algorithm to solve the problem in a transitive graph is proposed, wheren is the number of vertices. Based on the proposed algorithm the weighted version of a number of problems in VLSI layout (e.g.,k-layer topological via minimization), computational geometry (e.g., maximum multidimensionalk-chain), graph theory (e.g., maximumk-independent set in interval graphs), and sequence manipulation (e.g., maximum increasingk-subsequence) can be solved inO(kn ²), wheren is the input size.This Work was supported in part by the National Science Foundation under Grant MIP-8709074 and MIP-8921540.