几种CMOS VLSI的低功耗BIST技术

在分析全扫描内建自测试(BIST)较高测试功耗的基础上,总结出几种CMOS VLSI的低功耗BIST技术方案,包括减少待测电路(CUT)输入端的翻转次数、简化线性反馈移位寄存器(LFSR)结构、部分扫描低功耗BIST方法等.分析结果表明,这些方法不但在保证测试覆盖率的条件下,降低了测试平均功耗和峰值功耗,而且综合应用这几种方法将会使系统功耗指标达到最佳.     

An analog VLSI design for a neuron with a choice of learning rules

An analog implementation of a neuron using standard VLSI components is described. The node is capable of both delta-rule and simple error-correcting learning. Decomposition into functional blocks allows the parts of the design to be easily separated and understood. The connectivity problem is eased by serially encoding inputs so that all nodes in a layer are connected to a single line carrying activations from the previous layer. Performance implications of the architecture are considered. The design was simulated with the Spice transistor level simulator. Schemas for interconnection of large numbers of nodes and simulations of the circuitry required are presented. Results show that effective learning is achieved by both algorithms. Implementation of multiple learning rules in a single neuron is demonstrated as an effective way of increasing flexibility in neural network hardware implementations.     

Design and VLSI evaluation of a high-speed cellular array divider with a selection function

In recent years, very fast dividers have been required for the real-time application of digital signal processing, robot control, and the like. This paper proposes a high-speed cellular array divider with a selection function that is based on the non-restoring algorithm and can deal with both fixed-point and negative operands in two's complement form. This divider uses new techniques that can generate in parallel both the quotient bit of one row and a partial remainder and CLS bit of the next row. The delay time of the proposed divider is calculated in terms of a delay of one unit such as a NAND gate. Finally, by using PARTHENON, a CAD (computer-aided design) system for VLSI, this divider is designed and evaluated. As a result, elimination of the delay time for even rows becomes possible. Thus, the delay time can be decreased to approximately one half that of the high-speed divider proposed by Cappa and Hamacher, which uses the most general high-speed techniques of carry-save and CLA.     

Architecture Concepts for Multimedia Signal Processing

Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications, specific computational requirements are derived. It will be shown that multimedia applications benefit from an exhaustive and flexible exploitation of parallelism. Three architectural concepts—reconfigurable computing, simultaneous multithreading, and associative controlling—are presented, and their potential to increase further the performance on future multimedia applications is investigated.     

A High Speed VLSI Architecture for Handwriting Recognition

This article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and a straightforward interface with a hosting PC.HACRE has been fabricated and successfully tested at a clock frequency of 50 MHz. A board hosting up to four chips and providing a 33 MHz PCI interface has been manufactured and used to build BEATR IX, a system for the recognition of handwritten check amounts, by integrating image processing and neural network algorithms (on the board) with context analysis techniques (on the hosting PC).     

一种嵌入式协处理器的设计

文章介绍了嵌入式协处理器LSC87的结构和控制方式，LSC87为与Intel8087指令功能全兼容的嵌入式协处理器，研制中采用了Top-down完全正向设计流程，选择微程序作LSC87数据路径的控制以便于支持所有7种类型定浮点操作数与6种异常的屏蔽和非屏蔽处理，其中部分数据路径部件还组合了硬连线控制，使LSC87不仅对复杂操作的处理可控性好，而且有利于数值迭代计算的简单快速实现。     

VLSI布局布线及其划分算法的设计与实现

本文讨论在ＶＬＳＩ网络划分中应用的ｍｉｎｉ－ｃｕｔ算法，并根据实际运行情况提出一种改进的划分算法。     

VLSI design and implementation of a real-time image segmentation processor

Image segmentation is a crucial part of machine vision applications. In this paper a system to perform real-time segmentation of images is presented. It uses a real-time segmentation VLSI chip that is based on a gradient relaxation algorithm and is designed using the Path Programmable Logic design methodology developed at the University of Utah. The system design considerations, system specifications, and an input/output format for the chip are discussed. The actual design of the chip is given that uses pipeline methodology to achieve real-time performance with a compact VLSI layout. The implementation of the segmentation system is presented and the segmentation chip and the overall system are evaluated with regard to real-time performance and segmentation results.This work was supported in part by Grant ISI-856-0393 from the National Science Foundation.     

Infant mortality modelling for vlsi devices using graphical estimation

This paper presents a practical methodology for the routine analysis of VLSI infant mortality data. Device families are modelled using established graphical parameter estimation techniques, and the model parameters are applied to individual device types within the family. Burn-in requirements are calculated to achieve a desired early life reliability level. A technical summary of the methods is presented, and a small data set is analysed as an example. The analysis results from three large device families are also presented.