A theory of rectangular dual graphs

Arectangular graph is a plane graph where all regions are four-sided and all edges are oriented in either the vertical or the horizontal direction. In addition the graph enclosure must also be rectangular. Given a plane graph representing a desired component connectivity, itsrectangular dual can be used to build afloorplan. This indicates that a system implementation can allocate rectangular floorplan regions to components that can be pairwise connected through common borders.This paper proves that constructing a rectangular dual graph is equivalent to a matching problem in a bipartite graph derived from the given plane graph. A simple existence theorem in terms of the graph structure is obtained as a corollary.This work was supported by the National Science Council, Taiwan, Republic of China, under Contract NSC 78-0404-E006-14.     

BALANCED TRUNCATED MODELS OF C INTERCONNECT CIRCUITS AND THEIR SIMULATION

The Balanced Truncation Method (BTM) is applied to an even distributed RC interconnect case by using Wang's closed-forms of even distributed RC interconnect models. The results show that extremely high order RC interconnect can be high-accurately approximated by only third order balanced model. Related simulations are executed in both time domain and frequency domain. The results may be applied to VLSI interconnect model reduction and design.     

FPGA Implementation of a Pipelined On-Line Backpropagation

The paper describes the implementation of a systolic array for a multilayer perceptron with a hardware-friendly learning algorithm. A pipelined modification of the on-line backpropagation algorithm is shown and explained. It better exploits the parallelism because both the forward and backward phases can be performed simultaneously. The neural network performance for the proposed modification is discussed and compared with the standard so-called on-line backpropagation algorithm in typical databases and with the various precisions required. Although the preliminary results are positive, subsequent theoretical analysis and further experiments with different training sets will be necessary. For this reason our VLSI systolic architecture—together with the combination of FPGA reconfiguration properties and a design flow based on generic VHDL—can create a reusable, flexible, and fast method of designing a complete ANN on a single FPGA and can permit very fast hardware verifications for our trials of the Pipeline On-line Backpropagation algorithm and the standard algorithms.     

MPEG-4视频编码器象素压缩模块的VLSI结构设计

文章设计了一种基于MPEG-4的视频压缩编码器中象素压缩模块的VLSI结构。该设计采用分布算式结构——NEDA作为DCT变换的核心技术；应用基于LUT表结构使量化／反量化模块的设计简洁明了；同时对AC／DC预测模块还应用了新的存储策略，大大降低了FPGA中宝贵的存储空间。在满足处理速度和精度的要求下，利用了较少的晶体管数目和简洁的结构实现了象素压缩模块。     

门电路参数对互连线时延影响的仿真研究

文章推广了Wang氏RC梯形电路模型，对互连线阶跃响应上升时间与门电路参数的关系进行了仿真研究，给出了定量结果。门电路参数有输出电阻、输入电阻和电容。     

基于CORDIC算法并行FFT设计与硬件实现

讨论了复杂128点FFT处理器的并行和旋转结构。VLSI实现FFT适用于超高速数据处理。随着新的VLSI技术的发展，高速处理和低功耗设计成为现实。使用CORDIC旋转处理器可以优化面积和速度的设计，在不降低数据处理速度的基础上，这种FFT仅仅使用了5．3万等效逻辑门。     

Analog VLSI Circuits for Competitive Learning Networks

An investigation is made concerning implementations of competitive learning algorithms in analog VLSI circuits and systems. Analog and low power digital circuits for competitive learning are currently important for their applications in computationally-efficient speech and image compression by vector quantization, as required for example in portable multi-media terminals. A summary of competitive learning models is presented to indicate the type of VLSI computations required, and the effects of weight quantization are discussed. Analog circuit representations of computational primitives for learning and evaluation of distortion metrics are discussed. The present state of VLSI implementations of hard and soft competitive learning algorithms are described, as well as those for topological feature maps. Tolerance of learning algorithms to observed analog circuit properties is reported. New results are also presented from simulations of frequency-sensitive and soft competitive learning concerning sensitivity of these algorithms to precision in VLSI learning computations. Applications of these learning algorithms to unsupervised feature extraction and to vector quantization of speech and images are also described.     

Neuromorphic Synapses for Artificial Dendrites

We describe neuromorphic, variable-weight synapses onartificial dendrites that facilitate experimentation with correlativeadaptation rules. Attention is focused on those aspects of biologicalsynaptic function that could affect a neuromorphic network'scomputational power and adaptive capability. These include sublinearsummation, quantal synaptic noise, and independent adaptationof adjacent synapses. The diffusive nature of artificial dendritesadds considerable flexibility to the design of fast synapsesby allowing conductances to be enabled for short or for variablelengths of time. We present two complementary synapse designs:the shared conductance array and the self-timed synapse. Bothsynapse circuits behave as conductances to mimic biological synapsesand thus enable sublinear summation. The former achieves weightvariation by selecting different conductances from an on-chiparray, and the latter by modulating the length of time a constantconductance remains activated. Both work with our interchip communicationsystem, virtual wires. For the present purpose of comparing variousadaptation mechanisms in software, synaptic weights are storedoff chip. This simplifies the addition of quantal weight noiseand allows connections from different sources to the same dendriticcompartment to have independent weights.     

时域有限差分法分析数字信号传输线的耦合

超大规模数字电路的信号开关速度和集成度的提高，导致了信号波形变异和信号耦合问题，并要求用全波分析法才能给出准确结果。文中用时域有限差分法（FD－TD）分析了高速数字信号传输线的耦合特性，给出了经介质补偿后的结果。FD－TD方法中采用了完全匹配层（PML）吸收边界和电流源激励等最新研究结果。研究表明FD－TD方法是计算高速数字电路的有力工具。     

16×16位高速低功耗并行乘法器的实现

基于0.6μm双阱CMOS工艺模型,实现了一种高速低功耗16×16位并行乘法器。采用传输管逻辑设计电路结构,获得了低功耗的电路性能。采用改进的低功耗、快速Booth编码电路结构和4-2压缩器电路结构,它在2.5V工作电压下,运算时间达到7.18ns,平均功耗(100MHz)为9.45mW。