Si/InP键合界面的研究

应用疏水处理方法成功实现了Si/InP的键合,然后通过对InP和Si的表面XPS能谱分析得到界面信息,从而了解键合机理.I-V曲线也反应了键合界面的性质,通过450、550℃退火样品的伏安特性可知道,对于InP/Si键合结构而言,退火温度与界面特性应该存在最佳值.     

Si/Si直接键合界面热应力模型及模拟

根据Suhir的双金属带的热应力分布理论,建立了Si/Si直接键合界面应力模型,推导出了由于高温引起的正应力、剪切应力和剥离应力的解析方程。并且应用模拟软件Matlab对热应力进行了模拟,直观地表现了键合界面应力的大小及其分布情况,对键合工艺有一定的指导意义。     

Si/Si直接键合界面性质的研究

通过三步直接键合方法实现了 Si/ Si键合。采用 XPS、FTIR、I-V、拉伸强度等手段对 Si/ Si键合结构的界面特性作了深入广泛的研究。研究结果表明 ,高温退火后 ,在键合界面没有 Si-H和 Si-OH网络存在 ,键合界面主要由单质 Si和不定形氧化硅 Si Ox 组成。同时 ,研究还表明 ,I-V特性和键合强度强烈地依赖于退火温度。     

GaAs/Si晶圆片键合偏差及影响因素研究

针对化合物半导体与Si基晶圆异质集成中的热失配问题,利用有限元分析方法开展GaAs半导体与Si晶片键合匹配偏差及影响因素研究,建立了101.6 mm(4英寸)GaAs/Si晶圆片键合匹配偏差评估的三维仿真模型,研究了不同键合结构和工艺对GaAs/Si晶圆级键合匹配的影响,系统分析了键合温度、键合压力、键合介质厚度及摩擦特性等因素对键合偏差影响的规律。结果表明,键合压力和键合层摩擦系数对键合偏差的影响极大,并通过对上述因素的优化,其匹配偏差可控制到3μm以内。     

GaAs/Si直接键合用GaAs表面化学活化技术

研究了GaAs/Si疏水性直接键合技术中GaAs表面化学活化关键工艺,对比分析了不同体积分数的HF和HCl溶液作为表面活性处理剂时对GaAs表面进行活化处理的结果。发现用HCl和H2O溶液处理GaAs晶片得到的表面均方根粗糙度要优于用HF处理得到的结果,并且将处理过的GaAs晶片与Si片进行直接键合,发现用HCl进行表面活化的GaAs晶片与Si片键合的成功率要高于用HF进行表面活化的GaAs和Si键合。在200,300和400℃条件下,采用HCl和H2O体积比为1∶10的溶液处理的GaAs晶片与Si片都成功键合,并且200℃条件下键合后的界面质量较好。     

利用金属过渡层低温键合硅晶片

在Si/Si之间采用Ti/Au金属过渡层,实现了Si/Si低温键合,键合温度可低至414 ℃.采用拉伸强度测试对Si/Si键合结构的界面特性进行测试,结果表明,键合强度高于1.27MPa;I-V测试表明,Si/Ti/Au/Ti/Si键合界面基本为欧姆接触;X射线光电子能谱(XPS)测试结果进一步表明,界面主要为Si-Au共晶合金.不同温度的变温退火实验表明,键合温度越高,键合强度越大,且渐变退火有利于提高键合强度.     

Si/Ti/Au/Si键合技术研究及其应用

运用Si／Ti／Au／Au／Ti／Si在N2保护下及420℃左右，成功地实现了Au／Si共熔键合，成品率达到90％以上。该键合方法能进行选择区域键合，完全避免了由于Si／Si熔融键合过程中高温退火给微电子机械系统(MEMS)器件带来的畸变甚至失效，为新型室温红外探测器的研制奠定了良好的工艺基础，是此类结构MEMS器件的理想键合封装方法。     

Si/Si键合结构的电学性质测量及模拟

研究Si／Si键合的电学性质对于界面研究和微电子器件的制备有着重要意义。分析了亲水处理方法键合的不同Si／Si键合结构的I—V特性，然后用SOS模型对n—Si／n—Si的C—V特性做了计算机辅助模拟，并和实际C—V曲线比较得出了平带电压VFB和界面态密度Din，这些结果对于键合的界面性质的了解和研究都是有意义的。     

Si/GaAs晶圆片键合热应力及其影响因素分析

分别利用Suhir双金属带热应力分布理论和有限元法研究了Si/GaAs晶圆片键合界面在退火过程中的热应力分布,并将热应力分布理论计算结果与有限元分析结果进行了对比验证,得到了一致的结论.根据计算分析结果,对晶圆片进行了结构热变形分析,并研究了不同因素对键合热应力的影响,提出了减小键合热应力的有效措施.     

利用金属过渡层低温键合硅晶片

在Si/Si之间采用Ti/Au金属过渡层,实现了Si/Si低温键合,键合温度可低至414 ℃.采用拉伸强度测试对Si/Si键合结构的界面特性进行测试,结果表明,键合强度高于1.27MPa;I-V测试表明,Si/Ti/Au/Ti/Si键合界面基本为欧姆接触;X射线光电子能谱(XPS)测试结果进一步表明,界面主要为Si-Au共晶合金.不同温度的变温退火实验表明,键合温度越高,键合强度越大,且渐变退火有利于提高键合强度.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

n-GaAs和p-GaN晶片的直接键合

采用直接键合的方法成功实现了n-GaAs和p-GaN晶片的高质量键合.扫描电子显微镜观测结果表明,键合界面没有空洞.键合前后光致发光谱测试表明,键合工艺对材料质量影响不大.室温下界面的电流-电压特性表明,键合得到的n-GaAs/p-GaN异质结为肖特基二极管并且理想因子为1.08.n-GaAs和p-GaN材料直接键合的成功对于集成GaAs和GaN材料制备光电集成器件有重要意义.     

Kinetics of strain relaxation in semiconductor films grown on borosilicate glass-bonded substrates

Changes in the strain relaxation of semiconductor films due to growth on a thin epitaxial template bonded via a borosilicate glass to a mechanical handle wafer have been observed. Akinetic analysis of the mechanical decoupling between the film/template heterostructure and the handle wafer is developed in order to estimate and evaluate the contribution of glass viscous deformation to the observed strain relaxation. The thickness and elastic constants of the template and film, the thickness and viscosity of the bonding media, and the lateral dimension of the bonded structure are included in this model. Based on this model, the viscous flow of the glass is unlikely to have played a role in previous observations of changes in film strain relaxation due to growth on glass-bonded substrates. The calculations are used in conjunction with simple expressions for the temperature and composition dependence of borosilicate glass viscosity to result in design guidelines for substrate structures and annealing schedules in which the viscous flow of a borosilicate glass will contribute to the strain relaxation of a lattice-mismatched film.     

Yield challenges in wafer stacking technology

Wafer stacking technology offers a higher performance in a smaller size with a lower cost option for microelectronic industries. However, it suffers from a compound yield loss which becomes a key challenge and a limiting factor in this technology. A compound yield loss in wafer stacking has been analyzed and yield challenges have been presented. Assuming a random defect density per wafer and no yield fallout from stacking processes, the compound yield of a bonded wafer pair has been estimated with the most commonly used yield model. As a result, it is proposed that a die area reduction for wafer stacking is needed in order to offer a great yield advantage. Both wafer testing and wafer size are also proven to influence significantly a die yield in a bonded wafer pair.     

Direct wafer bonding of III-V compound semiconductors forfree-material and free-orientation integration

This paper describes the use of direct wafer bonding technique to implement the novel concept of “free-material and free-orientation integration” which we propose. The technique is applied for various wafer combinations of an InGaAsP material system, and the properties of the bonded structures are studied in terms of the crystalline and electrical characterization through transmission electron microscope, X-ray diffraction, and so on. This technique's advantage for use in the fabrication of lattice-mismatched structures is confirmed by the crystalline characterization, together with its second advantage of enabling bonded structures with an orientation mismatch, is investigated. The high crystalline quality of the bonded structures with both lattice and orientation mismatches is proved, and the electrical property of the bonded interface is examined for some of them. We show a practicability in a laser fabricated on a lattice- and orientation-mismatched structure by direct bonding. The results demonstrate the remarkable feasibility of using the direct wafer bonding technique to obtain integrated structures of material- and orientation-mismatched wafers with satisfactory quality     

Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%     

基于湿法表面活化处理的InP/SOI晶片键合技术

为了实现集成硅基光源,研究了基于湿法表面处理的InP/SOI直接键合技术。采用稀释的HF溶液对InP晶片进行表面活化处理,同时采用Piranha溶液对SOI晶片进行表面活化处理,实现了二者的低温直接键合。分别采用刀片嵌入法和划痕测试仪对样品的键合强度进行了定性及定量分析。同时,采用超声波扫描显微镜及扫描电子显微镜对键合界面的缺陷信息及键合截面的微观特性进行了评估。分析结果表明:提出的键合工艺可以获得较好的键合效果。     

Thermal and mechanical separations of silicon layers from hydrogen pattern-implanted wafers

A silicon layer was successfully transferred from a hydrogen pattern-implanted wafer to another by a thermal or mechanical cleavage process. The first wafer was masked with various patterns of 2.3 micron-thick poly-silicon, and was implanted at a hydrogen dose of 4,5, or 8 10¹⁶ cm⁻² with an energy of 150 keV or 180 KeV. After etching off the implantation mask, the wafer was bonded to a thermally grown oxide wafer face-to-face by low-temperature direct bonding. The bonded pair was then either heated (thermally) or bent (mechanically) until hydrogen-induced silicon layer cleavage occurred, resulting in the silicon layer transfer from the implanted wafer to the other. In this experiment, it was demonstrated that mechanical cleavage can overcome the fractional implantation area limination of thermal cleavage.     

表面翘曲度对晶圆直接键合的影响

根据薄板弯曲理论,推导出晶圆表面翘曲度及夹具形状影响晶圆直接键合的理论公式,很好地解释了晶圆材料性质及尺寸大小对直接键合的影响.利用理论公式比较了晶圆在外压力和无外压力作用下翘曲度对晶圆直接键合的不同影响,结果表明晶圆键合后的形状由晶圆的初始形状及键合所用的夹具决定.最后应用有限元进行了仿真分析,仿真结果表明,晶圆存在一定翘曲度时施加合适的外压力将有助于晶圆的直接键合.     

用于制备SOI材料的基于硅片键合和双层多孔硅剥离的薄外延硅膜转移技术

采用在阳极化反应时改变电流强度的办法 ,在高掺杂的 P型硅 (111)衬底上制备了具有不同多孔度的双层结构多孔硅层 .用超高真空电子束蒸发技术在多孔硅表面外延生长了一层高质量的单晶硅膜 .在室温下 ,该外延硅片同另一生长有热二氧化硅的硅片键合在一起 ,在随后的热处理过程中 ,键合对可在多孔硅处裂开 ,从而使外延的单晶硅膜转移到具有二氧化硅的衬底上以形成 SOI结构 .扫描电镜、剖面投射电镜、扩展电阻和霍尔测试表明 SOI样品具有较好的结构和电学性能