用有限元方法分析Si/GaAs的键合热应力

在考虑材料热膨胀系数随温度变化后,采用有限元方法结合ANSYS软件对Si/GaAs键合热应力进行了分析,研究了普通应力、轴向应力和剪切力的分布云图和沿界面的分布.同时提出了新的键合结构以减小热应力的影响,计算结果证明了该结构的有效性.     

用有限元方法分析Si/GaAs的键合热应力

在考虑材料热膨胀系数随温度变化后,采用有限元方法结合ANSYS软件对Si/GaAs键合热应力进行了分析,研究了普通应力、轴向应力和剪切力的分布云图和沿界面的分布.同时提出了新的键合结构以减小热应力的影响,计算结果证明了该结构的有效性.     

Analysis of Si/GaAs Bonding Stresses with the FiniteElement Method

在考虑材料热膨胀系数随温度变化后，采用有限元方法结合ANSYS软件对Si/GaAs键合热应力进行了分析，研究了普通应力、轴向应力和剪切力的分布云图和沿界面的分布. 同时提出了新的键合结构以减小热应力的影响，计算结果证明了该结构的有效性.     

表面翘曲度对晶圆直接键合的影响

根据薄板弯曲理论,推导出晶圆表面翘曲度及夹具形状影响晶圆直接键合的理论公式,很好地解释了晶圆材料性质及尺寸大小对直接键合的影响.利用理论公式比较了晶圆在外压力和无外压力作用下翘曲度对晶圆直接键合的不同影响,结果表明晶圆键合后的形状由晶圆的初始形状及键合所用的夹具决定.最后应用有限元进行了仿真分析,仿真结果表明,晶圆存在一定翘曲度时施加合适的外压力将有助于晶圆的直接键合.     

Ⅲ-Ⅴ族半导体晶片键合热应力分析

利用结构力学模型并且结合有限元方法,分析了InP/GaAs晶片键合时界面热应力的分布情况,理论分析结果和有限元结果一致,实验也证实了分析结果.最后详细讨论了减小晶片键合热应力的有关因素,对在热处理时提高晶片的键合质量提供一定的理论参考.     

InP/GaAs键合热应力的有限元分析

用有限元方法结合ANSYS工具,研究了InP/GaAs键合在退火后的热应力分布图像.重点计算并详细讨论了对解键合有重要作用的界面上的剥离力和剪切力.最后分析了影响热应力大小的有关因素.数值分析结果与相关文献实验结果一致.     

晶片键合界面应力分布的理论分析

根据双金属带的热应力分布理论,推导了晶片键合以及薄膜键合的界面应力分布公式.对影响晶片键合的剪切应力、正应力以及剥离应力的分布特性进行了讨论.     

表面残留颗粒对晶圆键合影响机制的研究

着重分析了晶圆表面残留颗粒对晶圆键合的影响,并从表面残留颗粒统计意义的角度,得到了一个晶圆键合的判定标准.为了改善键合界面出现的气泡问题,一种基于点压技术的新型点压键合法被应用到整片键合中,并和传统的金金热压键合法进行了比较.实验表明,采用点压键合法能够有效抑制晶圆表面残留颗粒对晶圆键合的影响.     

晶片键合界面应力分布的理论分析

根据双金属带的热应力分布理论,推导了晶片键合以及薄膜键合的界面应力分布公式.对影响晶片键合的剪切应力、正应力以及剥离应力的分布特性进行了讨论     

GaAs/Si晶圆片键合偏差及影响因素研究

针对化合物半导体与Si基晶圆异质集成中的热失配问题,利用有限元分析方法开展GaAs半导体与Si晶片键合匹配偏差及影响因素研究,建立了101.6 mm(4英寸)GaAs/Si晶圆片键合匹配偏差评估的三维仿真模型,研究了不同键合结构和工艺对GaAs/Si晶圆级键合匹配的影响,系统分析了键合温度、键合压力、键合介质厚度及摩擦特性等因素对键合偏差影响的规律。结果表明,键合压力和键合层摩擦系数对键合偏差的影响极大,并通过对上述因素的优化,其匹配偏差可控制到3μm以内。     

界面热应力对InP/Si键合质量的影响

通过实验和理论计算,分析了InP/Si键合过程中,界面热应力的分布情况、影响键合结果的关键应力因素及退火温度的允许范围。分析结果表明,由剪切应力和晶片弯矩决定的界面正应力是晶片中心区域大面积键合失败的主要原因,为保证良好的键合质量,InP/Si键合退火温度应该在300～350℃范围内选取。具体实验验证表明,该理论计算值与实验结果相一致。最后,在300℃退火条件下,很好地实现了2inInP/Si晶片键合,红外图像显示,界面几乎没有空洞和裂隙存在,有效键合面积超过90%。     

GaAs／GaAlAs阴极粘结工艺的X射线双晶衍射测量

分析了ＧａＡｓ／ＧａＡｌＡｓ阴极粘结工艺中应力产生的根源和晶体中应力对Ｘ射线双晶衍射峰的宽度和强度的影响。用Ｘ射线双晶衍射仪测量了阴极和玻璃热粘结工艺过程中阴极材料外延层和衬底的双晶回摆曲线。     

应用晶片键合技术制作激光器

针对于普通外延生长GaAs衬底激光器材料中存在的位错严重、热胀系数不匹配等问题,总结了国外键合工艺,将其应用于发光波长为850nm的AlGaAs脊波导量子阱激光器的制造,并提出了键合过程中各项关键步骤应注意的问题和解决方法.     

Modeling of Thermally Induced Stresses in Three-Dimensional Bonded Integrated Circuit Wafers

A finite-element model has been developed to investigate the potential reliability issues of thermally induced stresses in interwafer Cu via structures in three-dimensional (3D) integrated circuit (IC) wafers. The model is first partially validated by comparing computed results against experimental data on via test structures from planar ICs. Computed von Mises stresses show that the predicted failure agrees with the results of thermal cycle experiments. The model is then employed to study thermal stresses in interwafer Cu vias in 3D bonded IC structures. The results illustrate that there is a concern regarding the stability of interwafer Cu vias. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch length at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing bonding thickness.     

Interfacial thermal stresses in ACF bonding assembly

The interfacial stresses and chip cracking stress produced because of thermal and mechanical mismatch in layered electronic assembly are one of main reasons for the failure of electronic packages. The analytical model considering the nonlocal deformation of assembly was developed and applied to predict the interfacial stresses produced due to temperature variation for the short and long anisotropic conductive adhesive film (ACF) bonding assembly. The conditions of zero shear stress at the free ends and self-equilibrated peeling stresses were satisfied. Simultaneously the interfacial stresses of ACF assembly were also predicted by the corrected Suhir’s model, Wang’s model, Ghorbani’s model, local model and finite element model (FEM), which were compared with the results by the present model. In addition, the analytical expression of chip cracking stress was also obtained for layered electronic assembly. The approach is mathematically straightforward and can be extended to include the inelastic creep behavior.     

Thermal Stress Assessment for Transient Liquid-Phase Bonded Si Chips in High-Power Modules Using Experimental and Numerical Methods

The potential of transient liquid-phase (TLP) bonding for chip packaging applications has been evaluated, focusing on three interlayer arrangements (Ag-Sn-Ag, Ni-Sn-Ni, and Ag-Sn-Ni). Shear tests on TLP-bonded components provided the interlayer-dependent mechanical strength as well as failure mode and position. Critical local stresses, i.e., failure criteria, within the intermetallic compound (IMC) layer were derived by replicating the shear test conditions with finite-element methods. The missing coefficient of thermal expansion for Ag₃Sn IMC was obtained by producing small IMC bulk samples and subjecting them to dilatometric measurements. The experimental results were implemented into a finite-element model of a representative power module architecture to provide first predictions on thermally induced residual stresses that could be classified into fail/safe, as successfully validated by TLP chip bonding experiments. A numerical parameter study then assessed thermal stresses, including failure prediction and design optimization for TLP-bonded Si chips, considering the influence of process temperature, service conditions, TLP interlayer system, and metallization layers within the TLP joint. The presented procedure serves as a guideline to choose an appropriate TLP interlayer system for predefined boundary conditions, or vice versa.