LSC87中嵌入式ROM内建自测试实现

LSC87芯片是与Intel8086配套使用的数值协处理器，体系结构复杂，有较大容量的嵌入式ROM存储器，考虑到与Intel8087的兼容性和管脚的限制，必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现，然后提出了芯片中嵌入式ROM电路的内建自测试，着重介绍了内建自测试的设计与实现，并分析了采用内建自测试的误判概率，研究结果表明，文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销，获得了满意的故障覆盖率，大大提高了整个芯片的可测性。     

一种嵌入式SIMD协处理器地址产生器的设计

文章介绍了一种新的嵌入式SIMD协处理器地址产生器.该地址产生器主要完成地址计算和协处理器指令的场抽取功能.为了提高协处理器的性能,地址产生器中设计了新的传送路径.该传送路径能够不通过地址产生器中的ALU而把数据送入寄存器中,这个传送路径能够减少ldN指令的一个延迟周期.在SMIC0.18微米标准库单元下,该地址产生器的延迟能够满足周期为10ns的协处理器.     

基于FPGA的AES密码协处理器的设计和实现

文章基于FPGA设计了一种能完成AES算法加密的密码协处理器，设计中利用VirtexⅡ系列FPGA的结构特点，对AES算法的实现做了优化。实验证明，这种实现方式用较少的电路资源达到了较高的数据吞吐率。该密码协处理器还提供了和ARM处理器的接口逻辑，实现了用于加／解密和数据输入输出的协处理器指令．作为ARM微处理器指令集的扩展，大大提高了嵌入式系统处理数据加／解的效率，实现数据的安全传输。     

高速实时数据采集智能控制器的设计与实现

文章以嵌入式和数据采集技术为基础,研究设计并实现了基于ARM+FPGA体系架构面向高速实时数据采集应用的一种实用新型智能控制器。本文阐述了主处理器ARM最小系统、协处理器FPGA最小系统和ARM与FPGA通信接口等硬件系统技术的实现,以及Linux FPGA字符设备驱动程序开发、协处理器FPGA控制程序和主处理器ARM应用程序设计。智能控制器运用FPGA并行运算处理结构的优势,控制ADC进行高速数据采集。FPGA还可配置成软核处理器-Nios II嵌入式处理器,与ARM构成双核处理器系统。智能控制器通过ARM实现对FPGA的管理控制、实时数据采集和丰富外围接口的通信。     

基于高性能浮点乘累加器的浮点协处理器设计

复杂运算中经常需要处理取值范围大、精度高的浮点型数据,一般的低端嵌入式内核中没有浮点硬件单元,采用软件模拟浮点运算往往不能满足实时性要求。现研究基于高性能浮点乘累加的通用浮点协处理器设计与实现,重点研究提升浮点运算能力、减少硬件开销等关键技术。实验结果显示向量浮点协处理器运算周期减少40％以上。     

16位智能卡微控制器

16位智能卡微控制器AE45C1J01采用16位AE-4内核，具有MULTOS智能卡操作系统和SEED加密算法，包括196KB屏蔽ROM、36KB的EEPROM和6KB的片上RAM。具有协处理器、指数乘法／除法协处理器、DES加密协处理器，外设包括UART、2个定时器，     

基于灰度投影法的电子稳像平台设计与实现

研制了基于FPGA+ DSP架构的嵌入式实时电子稳像平台.DSP作为主处理器完成灰度投影稳像算法的运动估计和运动滤波,FPGA作为协处理器完成灰度投影数据累加及运动补偿.同时FPGA与内部Nios Ⅱ处理器还共同完成系统时序控制、视频编码器配置、视频解码器配置、图像采集显示控制、EMIF总线接口控制、图像帧存储等功能....     

低碳钢CO_2激光焊接光致等离子体屏蔽的实验研究

采用20kWCO2激光加工机焊接st37－2钢,研究了辅助气体种类、气体流量以及聚焦激光束的离焦状态对等离子体屏蔽的影响。结果表明,不同辅助气体时等离子体屏蔽临界功率密度存在很大差异,由小到大的顺序为：Ar→N2→CO2→He。He良好的控制等离子体的能力不仅在于He高的电离能不易形成LSC波,更主要地在于He良好的导热性能抑制了LSC波的扩展。增大辅助气体流量或采用负离焦均可以在一定程度上减小等离子体屏蔽对焊接过程的影响。     

应用安全协处理器构建一个金融终端中的安全嵌入式系统

本文主要介绍嵌入式系统应用需要安全机制与数据保护的重要性与DS5250所具独特的安全特性，并着重对应用DS5250安全协处理器构建一个金融终端中的安全嵌入式系统方案作分析说明。     

人机接口协处理器大力提升语音应用的性能

Spansion语音协处理器由定制型逻辑和高速存储器构成,并整合Nuanee公司的VOC0n软件引擎,为诸如语音之类的自然用户接口提供了一种专用资源,有利于加快和优化语音控制人机接口,同时还可消除常规CPU在处理语音数据时的工作负荷。     

嵌入式处理器的定点化运算单元设计

为了满足基于嵌入式处理器的音频解决方案的需要,提出了一种嵌入式处理器中高精度、多功能的定点化运算单元(FPU)。FPU由移位、舍入、饱和3个部分组成。通过对FPU的实现和验证,证明FPU能够显著提高嵌入式处理器定点化操作的速度。     

Application-specific programmable control for high-performanceasynchronous circuits

The advantages of the programmable control paradigm are widely known in the design of synchronous sequential circuits: easy correction of late design errors, easy upgrade of product families to meet time-to-market constraints, and modifications of the control algorithm, even at run time. However, despite the growing interest in asynchronous (self-timed) circuits, programmable asynchronous controllers based on the idea of microprogramming have not been actively pursued. In this paper, we propose an asynchronous microprogrammed control organization (called a microengine) that targets application-specific implementations and emphasizes simplicity, modularity, and high performance. The architecture takes advantage of the natural ability of self-timed circuits to chain actions efficiently without the clock-based scheduling constraints that would be involved in comparable synchronous designs. The result is a general approach to the design of application-specific microengines featuring a programmable data-path topology that offers very compact microcode and high performance-in fact, performance close to that offered by automated hardwired controllers. In performance comparisons of a CD-player error decoder design, the proposed microengine architecture was 26 times faster than the general purpose hardware of a 280 MIPS microprocessor, over three times as fast as the special purpose hardware of a low-power macromodule based implementation, and even slightly faster than a finite state machine-based implementation     

Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder

This paper demonstrates how IEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, and SRT divide operations and demonstrates that in every case a generic rounding architecture based on a prefix adder with a small amount of additional logic is sufficient to cover all the rounding modes. Critical path analysis shows that the proposed architecture is compatible with contemporary pipelined FPU design practice, while using significantly less logic     

Link Stability-Based Clustering and Routing in Ad-Hoc Wireless Networks Using Fuzzy Set Theory

An ad-hoc wireless network has multihop architecture and is more mobile than single-hop network architecture in the real world. But the ad-hoc wireless network has some challenge with respect to mobility, real-time communication, routing path, maintenance, spatial reuse, bandwidth management, and packets broadcast overhead. This paper investigates two important issues to ensure more stable path routing and less re-clustering to improve the system performance. Novel Linked Stability-Based Clustering (LSC) and Linked Stability-Based Routing (LSR) algorithms, using fuzzy set theory, are proposed. The LSC algorithm guarantees the stability of the cluster to reduce the probability of re-clustering because the cluster-head is not easily replaced. The LSC algorithm proposed in this paper reduces the easy re-clustering problem of the HCC algorithm by considering not only connectivity but also the link's signal strength between the mobile nodes obtained from a fuzzy set in cluster-head determination. The membership function of the LSC algorithm, based on the link's signal strength, predicts a more stable link routing path using fuzzy set theory. Simulation results show that the proposed algorithm ensures the stability of the cluster and avoids unnecessary re-clustering; for example, the LSC algorithm occurs less frequently than LID and HC algorithms. Similarly, the LSR routing algorithm that uses fuzzy sets and membership functions is based on the mean signal strength and the relative movement between nodes, to obtain the lifetime of each connection and the path lifetime, from fuzzy inferences and fuzzy rules for reference. The LSR algorithm provides more reliable path lifetime and more stable transmission than the table-driven or on-demand approaches. Simulation results reveal that the path lifetime of the LSR algorithm is longer than that of DSR, with a lower probability of path drop and avoiding rerouting. The LSR algorithm has a higher mean number of hoppings, because it always finds the most suitable path and is more stable than DSR, without searching again for a new path when the paths drop.     

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8-μm double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit     

A hierarchical network storage architecture for video-on-demandservices

The advances in cable TV networks and multimedia technologies have open the possibilities for network/service/content providers to offer residential customers with video-on-demand services. However, the mass storage system used in supporting such services demands proper organization and management. We present a three-level hierarchical network storage architecture for the video-on-demand storage system. At the first-level (local service center, LSC) a limited number of programs with high viewing probabilities are stored; while at the second-level (local central service center, LCSC) a few programs with the second highest viewing probabilities are stored. The third-level (central service center, CSC) contains all programs provided in the system. Based on this architecture and the program viewing probability distribution function, we use a minimum-cost function to find out the number of programs stored in the two service centers (LSC and LCSC) and the number of links among these three service centers. We also describe two program reallocation algorithms which swap programs between service centers according to the change in user request patterns     

Management of Logistic Support Costs in the Equipment Acquisition Phase

In recent years, a management concept known as design-to-cost has been implemented with considerable success by the US Department of Defense (DoD). Under this concept, a variety of system and equipment acquisition programs have incorporated an average unit production cost target in the development/production contract early in the development phase to control program costs throughout the development and production phases. Moreover, there has developed a widespread awareness of the need for broadening the design-to-cost concept to encompass operating and support (O&S) costs. The DoD and other government agencies have begun to use several contractual procedures for transmitting O&S cost goals to the contractor. One of these is called the ``logistic support cost (LSC) commitment'. The LSC commitment uses a LSC model as a basis for a cost target and subsequently a field cost measurement. This paper describes the management control objectives of the LSC commitment, considerations in implementing its strategy, and its statistical risks. Examples are presented and conclusions are drawn regarding the strengths and limitations of the LSC commitment as a life-cycle cost control device.     

Controlling Light Emission in Luminescent Solar Concentrators Through Use of Dye Molecules Aligned in a Planar Manner by Liquid Crystals

A luminescent solar concentrator (LSC) is a potential low‐cost enhancement of the standard large‐area silicon photovoltaic panels for the generation of electricity from sunlight. In this work, guest–host systems are investigated using anisotropic fluorescent dyes and liquid crystal mesogens to control the direction of emitted light in the LSC. It is determined that up to 30% more light is emitted from the edge of an LSC waveguide with planar dye alignment parallel to the alignment direction than from any edge of an LSC with no alignment (isotropic). The aligned samples continue to show dichroic performance after additions of both edge mirrors and rear scattering layer.     

先进音频编码中MDCT的新型递归结构及其FPGA设计

文章以新型的MDCT递归算法为基础，首先给出了一种主要模块分时共享、数据流同步多路处理的改进型并行处理结构，其可以高效地应用于国际音频标准MPEG-2以及MPEG-4的先进音频编码（AAC）当中。另外，针对递归实现结构高度模块化和较强规则性的特点，进行了FPGA的设计和仿真，结果表明：改进后的处理结构在增加少量硬件模块的条件下．大大提高了运算速度。