90nm CMOS工艺低功耗20GHz比较器设计

A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic （SCL） topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm^2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second （GSps） with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.     

一种用于热电堆传感器检测的55dB SNDR, 2.2mW 的双斩波稳定模拟前端电路

A double chopper-stabilized analog front-end （DCS-AFE） circuit for a thermopile sensor is presented, which includes a closed-loop front-end amplifier and a 2nd-order 1 bit quantization sigma-delta modulator. The amplifier with a closed-loop structure ensures the gain stability against the temperature. Moreover, by adopting the chopper-stabilized technique both for the amplifier and 2nd-order 1-bit quantization sigma-delta modulator, the low-frequency 1/f noise and offset is reduced and high resolution is achieved. The AFE is implemented in the SMIC 0.18 μm 1P6M CMOS process. The measurement results show that in a 3.3 V power supply, 1 Hz input frequency and 3KHz clock frequency, the peak signal-to-noise and distortion ratio （SNDR） is 55.4 dB, the effective number of bits （ENOB） is 8.92 bit, and in the range of -20 to 85 degrees, the detection resolution is 0.2 degree.     

8位12MS/s带片上参考电压的异步逐次逼近模数转换器

This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers.A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity.Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm.An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype,fabricated in UMC 0.18μm CMOS technology,achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s.The total power consumption is 0.918 mW for a 1.8 V supply,while the onchip reference consumes 53%of the total power.It achieves a figure of merit of 180 fJ/conv-step,excluding the reference’s power consumption.     

基于一种新架构的4GH 32比特的直接数字频率合成器

This paper presents a novel direct digital frequency synthesizer(DDFS)architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method,which has the advantages of high speed,low power and low hardware resources.By subdividing the sinusoid into a collection of phase segments,the same initial value of each segment is realized by a nonlinear DAC.The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method.Then,the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment.Meanwhile,the fine ROM stores the differences between the line values and the initial value of each line.A ROM compression ratio of32 can be achieved in the case of 11 bit phase and 9 bit amplitude.Based on the above method,a prototype chip was fabricated using 1.4 m GaAs HBT technology.The measurement shows an average spurious-free dynamic range(SFDR)of 45 dBc,with the worst SFDR only 40.07 dBc at a 4.0 GHz clock.The chip area is 4.6 3.7 mm2and it consumes 7 W from a–4.9 V power supply.     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

基于90nm CMOS工艺的一种10位低功耗SAR A/D转换器

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.     

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

FPGA Implementation of FFT Algorithm for OFDM Based IEEE 802.16d （Fixed WiMAX） Communications

The IEEE 802.16d communication standard uses orthogonal frequency division multiplexing （OFDM）. In the widely used OFDM systems, the fast Fourier transform （FFT） and inverse fast Fourier transform pairs are used to modulate and demodulate the data constellation on the sub-carriers. In this paper, a high level implementation of a high performance FFT for OFDM modulator and demodulator is presented. The design has been coded in Verilog and targeted into Xilinx Spartan3 field programmable gate arrays. Radix-22 algorithm is proposed and used for the OFDM communication system. The design of the FFT is implemented and applied to fixed WiMAX--IEEE 802.16d communi- cation standard. The results are tabulated and the hardware parameters are compared. The proposed architecture is least in number of multipliers used and the memory size, and second to the least in number of adders used.     

Four-bit all-optical quantization based on Raman self-frequency shift and spectral compression

An all-optical quantization based on Raman self-frequency shift（RSFS） in a photonic crystal fiber（PCF） and spectral compression in a dispersion-increasing fiber（DIF） is analyzed,and the evolution of femtosecond pulse in fibers is described by numerically solving the generalized nonlinear Schrdinge equation（GNLSE）.Gaussian pulse with the width of 300 fs and center wavelength of 1550 nm is injected into 15 m-long PCF and 100 m-long DIF.The simulation results show that the center wavelength increases linearly with the input peak power which changes from 110 W to 165 W.The RSFS of 65.3 nm and maximal spectral compression ratio of 3.38 can be obtained.The resolution of the quantization is improved from 2.4 bits to 4 bits by using the spectral compression in the DIF.     

Potentiality of semiconducting diamond as the base material of millimeter-wave and terahertz IMPATT devices

An attempt is made in this paper to explore the potentiality of semiconducting type-IIb diamond as the base material of double-drift region（DDR） impact avalanche transit time（IMPATT） devices operating at both millimetre-wave（mm-wave） and terahertz（THz） frequencies. A rigorous large-signal（L-S） simulation based on the non-sinusoidal voltage excitation（NSVE） model developed earlier by the authors is used in this study. At first,a simulation study based on avalanche response time reveals that the upper cut-off frequency for DDR diamond IMPATTs is 1.5 THz, while the same for conventional DDR Si IMPATTs is much smaller, i.e. 0.5 THz. The L-S simulationresultsshowthattheDDRdiamondIMPATTdevicedeliversapeakRFpowerof7.79Wwithan18.17%conversion efficiency at 94 GHz; while at 1.5 THz, the peak power output and conversion efficiency decrease to6.19mWand8.17%respectively,taking50%voltagemodulation.AcomparativestudyofDDRIMPATTsbasedon diamond and Si shows that the former excels over the later as regards high frequency and high power performance at both mm-wave and THz frequency bands. The effect of band to band tunneling on the L-S properties of DDR diamond and Si IMPATTs has also been studied at different mm-wave and THz frequencies.     

一种用于射频识别的超低功耗温度传感器

An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-μm CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 μA @ 1.8 V for continuous operation and achieves an accuracy of ±0.65 °C from –20 to 120 °C after calibration at one temperature.     

一种用于数字控制DC-DC转换器的近似时间最优轨迹预测法

The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC-DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC-DC with the proposed prediction is about 8/μs when the load current changes from 0.6 to 0.1A.     

采用后台数字校准的12位100MHz流水线模数转换器

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.     

一种适用于“模一”多带OFDM超宽带系统中跳频产生的3.96GHz锁相环

A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.     

Digital Signal Processing for Optical Access Networks

In this paper, we investigate advanced digital signal process ing （DSP） at the transmitter and receiver side for signal pre equalization and postequalization in order to improve spec trum efficiency （SE） and transmission distance in an optical access network. A novel DSP scheme for this optical super Nyquist filtering 9 Quadrature Amplitude Modulation （9 QAM） like signals based on muhimodulus equalization with out post filtering is proposed. This scheme recovers the Ny quist filtered Quadrature PhaseShift Keying （QPSK） signal to a 9QAMlike one. With this technique, SE can be increased to 4 b/s/Hz for QPSK signals. A novel digital superNyquist signal generation scheme is also proposed to further suppress the Nyquist signal bandwidth and reduce channel crosstalk without the need for optical prefiltering. Only optical cou plers are needed for superNyquist wavelengthdivisionmulti plexing （WDM） channel multiplexing. We extend the DSP for shorthaul optical transmission networks by using highorder QAMs. We propose a highspeed Can＇ierless Amplitude/Phase 64 QAM （CAP64 QAM） system using directly modulated la ser （DML） based on direct detection and digital equalization. Decisiondirected least mean square is used to equalize the CAP64QAM. Using this scheme, we generate and transmit up to 60 Gbit/s CAP64QAM over 20 km standard single mode fiber based on the DML and direct detection. Finally, several key problems are solved for real time orthogonalfre quencydivisionmultiplexing （OFDM） signal transmission aml processing. With coherent detection, up to 100 Glfit/s 16 QAMOFDM realtime transmission is possible.     

应用于低中频和零中频DVB调谐器中8阶信道滤波器设计

An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves -52 dB and the out-band IM3 achieves -55 dB with -11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18μm CMOS process, consumes 4 mA current with 1.8 V power supply.     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter（ADC） designed in a 0.5-μm CMOS process.Adopting the global and local bias scheme,the number of interconnect signal lines is reduced numerously,and the ADC exhibits the advantages of scalability and portability.Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process;thus,it is suitable for applications in the system on one chip（SoC） design as an analogue IP.Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 μA.Adopting the histogram testing method,the ADC was tested in a 3.3 V supply voltage/±64 μA quantization range and a 5 V supply voltage/±256 μA quantization range,respectively.The results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB,DNL/INL are-0.005 to ＋0.027 LSB/-0.1 to ＋0.2 LSB,respectively,under a 5 V supply voltage with a digital error correction technique.     

具有频率调谐的GNSS接收机双模复数滤波器

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18μm CMOS process.This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz.A fully differential OTA with source degeneration is used to provide sufficient linearity.Furthermore,a ring CCO based frequency tuning scheme is proposed to reduce frequency variation.The measured results show that in narrow-band mode the image rejection ratio（IMRR）is 35 dB,the filter dissipates 0.8 mA from the 1.8 V power supply,and the out-of-band rejection is 50 dB at 6 MHz offset.In wide-band mode,IMRR is 28 dB and the filter dissipates 3.2 mA.The frequency tuning error is less than±2%.     

Attribute Based DRM Scheme with Dynamic Usage Control in Cloud Computing

In order to achieve fine-grained access control in cloud computing, existing digital rights management （DRM） schemes adopt attribute-based encryption as the main encryption primitive. However, these schemes suffer from inefficiency and cannot support dynamic updating of usage rights stored in the cloud. In this paper, we propose a novel DRM scheme with secure key management and dynamic usage control in cloud computing. We present a secure key management mechanism based on attribute-based encryption and proxy re-encryption. Only the users whose attributes satisfy the access policy of the encrypted content and who have effective usage rights can be able to recover the content encryption key and further decrypt the content. The attribute based mechanism allows the content provider to selectively provide fine-grained access control of contents among a set of users, and also enables the license server to implement immediate attribute and user revocation. Moreover, our scheme supports privacy-preserving dynamic usage control based on additive homomorphic encryption, which allows the license server in the cloud to update the users＇ usage rights dynamically without disclosing the plaintext. Extensive analytical results indicate that our proposed scheme is secure and efficient.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.