A baseband LPF for GSM,TD-SCDMA and WCDMA multi-mode transmitters

This paper describes a low-pass reconfigurable baseband filter for GSM,TD-SCDMA and WCDMA multi-mode transmitters.To comply with 3GPP emission mask and limit TX leakage at the RX band,the out-of -band noise performance is optimized.Due to the distortion caused by the subthreshold leakage current of the switches used in capacitor array,a capacitor bypass technique is proposed to improve the filter’s linearity.An automatic frequency tuning circuit is adopted to compensate the cut-off frequency variation.Simulation results show that the filter achieves an in-band input-referred third-order intercept point(IIP3) of 47 dBm at 1.2-V power supply and the out-of-band noise can meet TX SAW-less requirement for WCDMA & TD-SCDMA.The baseband filter incorporates -40 to 0 dB programmable gain control that is accurately variable in 0.5 dB steps.The filter’s cut-off frequency can be reconfigured for GSM/TD-SCDMAAVCDMA multi-mode transmitter.The implemented baseband filter draws 3.6 mA from a 1.2-V supply in a 0.13μm CMOS process.     

A pseudo differential Gm-C complex filter with frequency tuning for IEEE802.15.4 applications

This paper presents a CMOS G_m-C complex filter for a low-IF receiver of the IEEE802.15.4 standard.A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator.A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated.The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately.The chip was fabricated in a standard 0.35μm CMOS process,with a single 3.3 V power supply.The filter consumes 2.1 mA current,has a measured in-band group delay ripple of less than 0.16μs and an IRR larger than 28 dB at 2 MHz apart,which could meet the requirements of the IEEE802.15.4 standard.     

具有频率调谐的GNSS接收机双模复数滤波器

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18μm CMOS process.This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz.A fully differential OTA with source degeneration is used to provide sufficient linearity.Furthermore,a ring CCO based frequency tuning scheme is proposed to reduce frequency variation.The measured results show that in narrow-band mode the image rejection ratio（IMRR）is 35 dB,the filter dissipates 0.8 mA from the 1.8 V power supply,and the out-of-band rejection is 50 dB at 6 MHz offset.In wide-band mode,IMRR is 28 dB and the filter dissipates 3.2 mA.The frequency tuning error is less than±2%.     

一款用于数字电视调谐器的高线性度多频带增益可调信道选择滤波器

This paper presents a channel-select filter that employs an active-RC bi-quad structure for TV-tuner application. A design method to optimize the IIP3 of the bi-quad is developed. Multi-band selection and gain adjustment are implemented using switching resistors in the resistor array and capacitors in the capacitor array. Q-factor degradation is compensated by a tuning segmented resistor. A feed-forward OTA with high gain and low third-order distortion is applied in the bi-quad to maximize linearity performance and minimize area by avoiding extra compensation capacitor use. An RC tuning circuit and DC offset cancellation circuit are designed to overcome the process variation and DC offset, respectively. The experimental results yield an in-band IIP3 of more than 31 dBm at 0 dB gain, a 54 dB gain range with 6 dB gain step, and a continuous frequency tuning range from 0.25 to 4 MHz. The in-band ripple is less than 1.4 dB at high gain mode, while the gain error and frequency tuning error are no more than 3.4% and 5%, respectively. The design, which is fabricated in a 0.18 μm CMOS process, consumes 12.6 mW power at a 1.8 V supply and occupies 1.28 mm2.     

一种用于无线接收机的噪声整形可重构复数带通/低通滤波器的设计

A reconfigurable complex band-pass （CBP）/low-pass （LP） active-RC filter with a noise-shaping technique for wireless receivers is presented. Its bandwidth is reconfigurable among 500 kHz, 1 MHz and 4 MHz in LP mode and 1 MHz, 2 MHz and 8 MHz in CBP mode with 3 MHz center frequency. The Op-Amps used in the filter are realized in cell arrays in order to obtain scalable power consumption among the different operation modes. Furthermore, the filter can be configured into the 1st order, 2nd order or 3rd order mode, thus achieving a flexible filtering property. The noise-shaping technique is introduced to suppress the flicker noise contribution. The filter has been implemented in 180 nm CMOS and consumes less than 3 mA in the 3rd 8 MHz-bandwidth CBP mode. The spot noise at 100 Hz can be reduced by 14.4 dB at most with the introduced noise-shaping technique.     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.     

一种用于短距离器件的433/868 MHz的带I/Q校准的低中频接收机

A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.     

A continuously and widely tunable analog baseband chain with digital-assisted calibration for multi-standard DBS applications

This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/Hz^1/2.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.     

一种用于短距离无线通信的低功耗多频带可配置收发机

A reconfigurable multi-mode multi-band transceiver for low power short-range wireless communication applications is presented.Its low intermediate frequency(IF) receiver with 3 MHz IF carrier frequency and the direct-conversion transmitter support reconfigurable signal bandwidths from 250 kHz to 2 MHz and support a highest data rate of 3 Mbps for MSK modulation.An integrated multi-band PLL frequency synthesizer is utilized to provide the quadrature LO signals from about 300 MHz to 1 GHz for the transceiver multi-band application. The transceiver has been implemented in a 0.18μm CMOS process.The measurement results at the maximum gain mode show that the receiver achieves a noise figure(NF) of 4.9/5.5 dB and an input 3rd order intermodulation point(IIP3) of-19.6/-18.2 dBm in 400/900 MHz band.The transmitter working in 400/900 MHz band can deliver 10.2/7.3 dBm power to a 50Ωload.The transceiver consumes 32.9/35.6 mW in receive mode and 47.4/50.1 mW in transmit mode in 400/900 MHz band,respectively.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

Survivable Virtual Network Mapping Using Optimal Backup Topology in Virtualized SDN

Software-Defined Network architecture offers network virtualization through a hypervisor plane to share the same physical substrate among multiple virtual networks. However, for this hypervisor plane, how to map a virtual network to the physical substrate while guaranteeing the survivability in the event of failures, is extremely important. In this paper, we present an efficient virtual network mapping approach using optimal backup topology to survive a single link failure with less resource consumption. Firstly, according to whether the path splitting is supported by virtual networks, we propose the OBT-I and OBT-II algorithms respectively to generate an optimal backup topology which minimizes the total amount of bandwidth constraints. Secondly, we propose a Virtual Network Mapping algorithm with coordinated Primary and Backup Topology （VNM-PBT） to make the best of the substrate network resource. The simulation experiments show that our proposed approach can reduce the average resource consumption and execution time cost, while improving the request acceptance ratio of VNs.     

Large-signal characterizations of DDR IMPATT devices based on group Ⅲ-Ⅴ semiconductors at millimeter-wave and terahertz frequencies

Large-signal （L-S） characterizations of double-drift region （DDR） impact avalanche transit time （IM- PATT） devices based on group III-V semiconductors such as wurtzite （Wz） GaN, GaAs and InP have been carried out at both millimeter-wave （mm-wave） and terahertz （THz） frequency bands. A L-S simulation technique based on a non-sinusoidal voltage excitation （NSVE） model developed by the authors has been used to obtain the high frequency properties of the above mentioned devices. The effect of band-to-band tunneling on the L-S properties of the device at different mm-wave and THz frequencies are also investigated. Similar studies are also carried out for DDR IMPATTs based on the most popular semiconductor material, i.e. Si, for the sake of comparison. A compara- tive study of the devices based on conventional semiconductor materials （i.e. GaAs, InP and Si） with those based on Wz-GaN shows significantly better performance capabilities of the latter at both mm-wave and THz frequencies.     

Distributed Power Control for Energy Conservation in Hybrid Cellular Network with Device-to-Device Communication

Device-to-Device （D2D） com- munication has been proposed as a promising implementation of green communication to benefit the existed cellular network. In order to limit cross-tier interference while explore the gain of short-range communication, we devise a series of distributed power control （DPC） schemes for energy conservation （EC） and enhancement of radio resource utilization in the hybrid system. Firstly, a constrained opportunistic power control model is built up to take advantage of the interference avoidance methodology in the presence of service requirement and power constraint. Then, biasing scheme and admission control are added to evade ineffective power consumption and maintain the feasibility of the system. Upon feasibility, a non-cooperative game is further formulated to exploit the profit in EC with minor influence on spectral efficiency （SE）. The convergence of the DPC schemes is validated and their performance is confirmed via simulation results.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A K-Median Facility Location Agent for Low-Cost Service Selection in Digital Community Network

With the increasing number of web services, it becomes a difficult task for an ordinary user to select an appropriate service. Hence, it is conventional that users in a digital community network take part in a collaborative mechanism for the purpose of service selection. The participation usually brings unnecessary burdens for users, such as giving opinions, storing service information. Extra communication overhead hinders the performance of the network. Thus, the community administrators are facing a problem of how to obtain an overall service selection result for the whole community readily and effectively. To address this problem, we present a k-median facility location agent model. The model analyzes the procedure of service selection through five entities and six types of messages. Two algorithms are elaborated in pursuit of a global optimization concerning connection costs between users and facilities where services are deployed. To evaluate our model, we conduct extensive simulations and present a detailed analysis of the simulation results.     

一种适用于“模一”多带OFDM超宽带系统中跳频产生的3.96GHz锁相环

A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.