A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.     

OFDM超宽带3.1-4.8GHz CMOS发射机设计

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的低功耗射频CMOS发射机芯片的设计和实现。发射机系统主要由电压电流跨导级、正交上变频调制器、有源双转单转换器、输出增益可控功率放大器以及产生正交差分LO信号的除2除法器等模块组成。使用上调制器,双转单及输出放大器分段谐振技术解决3.1-4.8GHz宽带增益平坦度问题;使用源级电阻负反馈镜像跨导解决系统低电压高线性度问题;使用无源电感谐振双转单电路及增益可控放大器进行低功耗设计。测试结果表明,芯片能够提供-10.7到-3.1dBm的功率输出,并且在子带增益平坦度低于3dB;输出三阶交调量最高可达12dBm;不低于30dBc的载波抑制和35dBc以上的边带抑制。芯片采用Jazz 0.18μm射频CMOS工艺流片,包括ESD防护PAD在内芯片总面积为1.74mm2。 在1.8V的电源电压下,芯片总电流为32mA。     

一种用于3.1–4.8GHz MB-OFDM 超宽带系统的CMOS接收机

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的全集成全差分CMOS接收机芯片。在接收机射频前端中应用了一种增益可变的低噪声放大器和合并结构的正交混频器。在I/Q中频通路中则集成了5阶Gm-C结构的有源低通滤波器以及可变增益放大器。芯片通过Jazz 0.18μm RF CMOS工艺流片,含ESD保护电路。该接收机最大电压增益为65dB,增益可调范围为45dB,步长6dB;接收机在3个频段的平均噪声系数为6.4-8.8dB,带内输入三阶交调量(IIP3)为-5.1dBm。芯片面积为2.3平方毫米,在1.8V电压下,包括测试缓冲电路和数字模块在内的总电流为110mA。     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

适用于OFDM UWB 系统的低功耗，大锁定范围注入锁定分频器

This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz （6.23 to 11.08 GHz） at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm^2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.     

闽西地区混凝土结构耐久性现状分析——以三明市为例

对影响三明市混凝土耐久性的因素进行分析,并对该地区结构耐久性状况进行判定,同时提出相关的建议及措施.     

OFDM超宽带3.1-4.8GHz CMOS射频收发机设计

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的CMOS射频收发机芯片的设计和实现。射频收发机采用零中频结构,主要模块包括：增益可控的宽带低噪声放大器、正交跨导复用下变频混频器、5阶Gm-C切比雪夫低通滤波器及可变增益放大器;采用多项滤波器进行边带杂散抑制的快速跳变频率综合器;宽带线性上变频正交调制器、片内有源双转单电路及输出可变增益放大器。芯片测试结果表明,接收机最大能够获得68dB的电压增益,其中42dB为可变增益,增益步长为6dB;在三个子带内的噪声系数为5.5~8.8dB;带内IIP3和带外IIP3不低于-4dBm和9dBm;发射机能够提供-10.7~-3dBm的输出功率,7.7dB的增益可控;输出1dB压缩点不低于-7.7dBm;发射信号边带抑制为32.4dBc,载波泄漏抑制可达31.1dBc;频率综合器的快速跳边时间低于2.05nS。芯片采用Jazz 0.18μm射频CMOS工艺流片,包括ESD防护PAD在内芯片总面积为6.1mm2;在1.8V的电源电压下,整个芯片的工作电流为221mA (RX+TX+SYN+Buffers）。     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

正A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm~2 and draws a total current of 221 mAfrom 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_(1dB) better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

超宽带系统CMOS全集成射频收发器设计

本文介绍3.1-4.8GHz MB-OFDM系统的CMOS射频收发器。电路采用直接变频架构,由接收器、发射器和频率综合器组成。采用PGS隔离技术和其他隔离措施完成了单片射频收发器的版图布局。后仿真结果表明,接收链路可提供的最大增益为72dB,其52dB为可变增益,三个子频带内噪声系数介于5.2-7.8dB,带外IIP3不低于-3.4dBm。发射链路可提供的可控输出功率-8dBm到-2dBm,输出1dB压缩点不低于4dBm,输出信号边带抑制约44dBc,载波抑制不低于34dBc。频率综合器在三个频点间的跳变时间小于9ns。芯片采用Jazz0.18μm射频CMOS工艺设计,面积为6.1mm2。在1.8V电源电压下,总电流约221mA。