| 一种适用于“模一”多带OFDM超宽带系统中跳频产生的3.96GHz锁相环 |
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| 引用本文： | 郑永正,李伟男,夏玲琍,黄煜梅,洪志良.一种适用于“模一”多带OFDM超宽带系统中跳频产生的3.96GHz锁相环[J].半导体学报,2009,30(7):075003-5. |
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| 作者姓名： | 郑永正 李伟男 夏玲琍 黄煜梅 洪志良 |
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| 摘 要： | A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.
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| 关 键 词： | 自适应跳频 OFDM 超宽带 锁相回路 载波 GHz 锁相环路 CMOS工艺 |
| 修稿时间： | 2/2/2009 12:00:00 AM |
A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation |
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| Zheng Yongzheng,Li Weinan,Xia Lingli,Huang Yumei and Hong Zhiliang.A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation[J].Chinese Journal of Semiconductors,2009,30(7):075003-5. |
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| Authors: | Zheng Yongzheng Li Weinan Xia Lingli Huang Yumei and Hong Zhiliang |
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| Affiliation: | State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China;State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China;State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China;State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China;State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China |
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| Abstract: | phase-locked loop adaptive frequency calibration loop filter CMOS UWB |
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| Keywords: | phase-locked loop adaptive frequency calibration loop filter CMOS UWB |
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