用遗传算法实现逻辑函数的化简

在硬件设计中引入演化计算，在可编程逻辑器件上通过对基本硬件元器件进行演化而自动生成人工难以设计出的硬件结构，称为演化硬件设计。代数法和卡诺图法用来化简给定的逻辑函数，但它们难以化简规模很大的逻辑函数。这里用演化硬件设计方法实现了区别于传统的代数化简法和卡诺图化简法的一种新的对给定的某一逻辑函数进行化简的方法。实验表明演化硬件设计方法能够化简规模很大的逻辑函数。     

基于演化算法的电路自动设计方法

在电路设计中引入演化计算,在可编程逻辑器件上通过对基本电路元器件进行演化而自动生成人工不可能设计出的电路结构,称为演化硬件设计。文中介绍了演化硬件实现的物质基础、演化计算在硬件自动设计方法的实现过程以及该方法要解决的问题,并对演化数字电路、模拟电路的设计进行了分析,说明演化算法在电路自动设计中是切实有效的。     

演化硬件技术及其应用发展

在硬件电路设计中引入演化计算,在可编程逻辑器件上通过对基本电路元器件进行演化而自动生成人工不可能设计出的电路结构,称为演化硬件设计。本文就演化硬件的原理和其国内外的发展现状进行说明和阐述,并对此技术的具体实现过程做了一个简单的实验。通过实验,说明演化硬件技术确实在电路自动设计方面有着极大的前景。最后介绍了演化硬件技术发展,及其应用到深空探测领域的现实意义。     

模块机器人及计算机辅助设计

本文利用新一代计算机辅助设计方法,开展模块机器 人的设计方法论和CAD系统的研究,旨在提出解决柔性加工系统的计算机辅助设计智能软件 的思路和框架．本文以模块机器人的设计为突破口,提出了以面向任务为特征、基于事例的 设计方法在机械概念化设计中的应用．论文中介绍了近年来发展迅速的模块机器人的标准模 块和基本拓扑关系,根据模块机器人概念化设计的特征,结合人工智能应用中基于事例的推 理机制,提出了面向任务和基于事例的计算机辅助设计方法和应用软件的框架,以及实现自 上而下的计算机推理的流程．文中还介绍了面向用户的机器人任务和工作环境的表示．     

Evolvable Hardware in Evolutionary Robotics

In recent decades the research on Evolutionary Robotics (ER) has developed rapidly. This direction is primarily concerned with the use of evolutionary computing techniques in the design of intelligent and adaptive controllers for robots. Meanwhile, much attention has been paid to a new set of integrated circuits named Evolvable Hardware (EHW), which is capable of reconfiguring its architectures unlimited time based on artificial evolution techniques. This paper surveys the application of evolvable hardware in evolutionary robotics. The evolvable hardware is an emerging research field concerning the development of evolvable robot controllers at the hardware level to adapt to dynamic changes in environments. The context of evolvable hardware and evolutionary robotics is reviewed, and a few representative experiments in the field of robotic hardware evolution are presented. As an alternative to conventional robotic controller designs, the potentialities and limitations of the EHW-based robotic system are discussed and summarized.     

Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs

This paper presents a methodology for the realization of intelligent, task-based reconfiguration of the computational hardware for mobile robot applications. Task requirements are first partitioned into requirements on the system hardware and software. Architecture is proposed that enables these requirements to be addressed through appropriate hardware and software components. Hardware–software co-design and hardware reconfiguration are utilized to design robotic systems that are fault-tolerant and have improved reliability. It is shown that this design enables the implementation of efficient controllers for each task of the robot thereby permitting better operational efficiency using fixed computational resources. The approach is validated through case studies where a team of robots is configured and the behavior of the robots is dynamically modified at run-time. It is demonstrated through this implementation that the design procedure results in increased flexibility in configuration at run-time. The ability to reconfigure the resources also aids collaboration between robots, and results in improved performance and fault tolerance.     

基于演化硬件的在线自适应系统

随着演化硬件的兴起,其在电子电路自动设计、客错以及自适应等方面的优越性,使它有望成为突破传统电子系统设计瓶颈的新技术.在已有研究的基础之上,进一步探讨利用演化硬件技术实现电子系统的自适应性,提出了一个基于演化硬件技术的自适应系统模型,并通过在Xilinx Virtex-Ⅱ Pro (XC2VP20)FPGA芯片上的实验,表明了演化硬件技术是解决电子系统自适应性问题的一种可行方案.     

Designing intelligent litigation support tools: The IKBALS perspective

In the legal domain, it is rare to find solutions to problems by simply applying algorithms or invoking deductive rules in some knowledge‐based program. Instead, expert practitioners often supplement domain‐specific knowledge with field experience. This type of expertise is often applied in the form of an analogy. This research proposes to combine both reasoning with precedents and reasoning with statutes and regulations in a way that will enhance the statutory interpretation task. This is being attempted through the integration of database and expert system technologies. Case‐based reasoning is being used to model legal precedents while rule‐based reasoning modules are being used to model the legislation and other types of causal knowledge. It is hoped to generalise these findings and to develop a formal methodology for integrating case‐based databases with rule‐based expert systems in the legal domain.     

Real-world applications of analog and digital evolvable hardware

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITI's Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation     

Evolvable hardware: using evolutionary computation to design and optimize hardware systems

Evolvable hardware lies at the intersection of evolutionary computation and physical design. Through the use of evolutionary computation methods, the field seeks to develop a variety of technologies that enable automatic design, adaptation, and reconfiguration of electrical and mechanical hardware systems in ways that outperform conventional techniques. This article surveys evolvable hardware with emphasis on some of the latest developments, many of which deliver performance exceeding traditional methods. As such, the field of evolvable hardware is just now starting to emerge from the research laboratory and into mainstream hardware applications.     

A case-based reasoning system for PCB defect prediction

The manufacturing process for a new Printed Circuit Board (PCB) design is often instable and might generate a number of defects during the complicated production process. Defects reduce the yield rate and increase the production costs. Although skilled engineers can predict the possible defect items for a new PCB product, this approach requires strong engineering experience and is time consuming. To conquer this problem, this research applies case-based reasoning (CBR) methodology to develop a defect prediction system for new PCB products. In the CBR system, each case is represented using the design specifications, defect items and corresponding costs. A vantage-based case indexing mechanism is developed to accelerate the case retrieval efficiency. In addition, a reasoning algorithm that considers the defect cost is proposed to infer the defect items that are interesting to PCB manufacturers. The system performance is analyzed to show the efficiency and accuracy of the proposed system. A practical implementation using a case-base provided by a PCB manufacturer is demonstrated.     

综合推理与智能书法创作

In this paper, we address the demanding task of developing intelligent systems equipped with machine creativity that can perform design tasks automatically. The main challenge is how to model human beings' creativity mathematically and mimic such creativity computationally. We propose a ``synthesis reasoning model" as the underlying mechanism to simulate human beings' creative thinking when they are handling design tasks. We present the theory of the synthesis reasoning model, and the detailed procedure of designing an intelligent system based on the model. We offer a case study of an intelligent Chinese calligraphy generation system which we have developed. Based on implementation experiences of the calligraphy generation system as well as a few other systems for solving real-world problems, we suggest a generic methodology for constructing intelligent systems using the synthesis reasoning model.     

Evolvable hardware techniques for on-chip automated reconfiguration of programmable devices

While complete automated design is a harder problem than computer-assisted design, automated hardware reconfiguration is an even more challenging problem, because it needs to adjust to limited resources and various factors, such as noise and parasitic capacitance, a resistance and inductance. This paper presents some experimental results of on-chip automated design and reconfiguration using evolvable hardware techniques. It describes a stand-alone board level evolvable system, and its use to demonstrate on-chip synthesis of new circuits in only a few seconds. The experiments presented here indicate a recovery capability in the case of extreme environmental conditions, such as extreme temperatures, that adversely affect electronics. Some of the difficulties of dealing with the real hardware are exposed, as well as challenges more generally related to automated evolution of complex electronic systems.The work described in this paper was performed at the Center for Integrated Space Microsystems, Jet Propulsion Laboratory, California Institute of Technology and was sponsored by the Defense Advanced Research Projects Agency and by the National Aeronautics and Space Administration.     

使用常规IC的演化硬件电路设计实例

在讨论了EHW运行机制及其在一般硬件实验环境中所面临问题的基础上，具体针对一种分频电路进行了基于常规计算设备和普通TTL芯片的演化研究和具体实现，进而完成了能以闭环方式进行系统演化的实验环境；运行结果表明，该方式既从原理上保留了演化硬件的全部特点，又在一定程度上摆脱了对FPGA等类型可编程芯片和相关软件环境的依赖，可以在此基础之上有效地进行多种演化策略和演化方式的研究，具有一定的实用价值。     

Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform

Finite impulse response filters (FIRs) are crucial devices for robust data communication and manipulation. Multiplierless filters have been shown to produce high performance systems with fast signal processing and reduced area. Furthermore, the distributed architecture inherent in multiplierless filters makes it a suitable candidate for fault tolerant design. Alternative approaches to the design of fault tolerant systems have been proposed using evolutionary algorithms (EAs) and the concept of evolvable hardware (EHW). This paper presents an evolvable hardware platform for the automated design and adaptation of multiplierless digital filters. Filters are realised within a dedicated programmable logic array (PLA) based on the Primitive Operator Filter design principle. The platform employs a genetic algorithm to autonomously configure the PLA for a given set of coefficients. The ability of the platform to adapt to increasing numbers of faults was investigated through the evolution of a 31-tap low-pass FIR filter. Results show that the functionality of filters evolved on the PLA was maintained despite an increasing number of faults covering up to 25% of the PLA area. Additionally, three PLA initialisation methods were investigated to ascertain which produced the fastest fault recovery times. It was shown that seeding a population of random configuration-strings with the best configuration currently obtained resulted in a 6 fold increase in fault recovery speed over other methods investigated.     

A methodology for efficient hardware verification

We present a methodology which helps structure the design and verification of hardware circuits. Our methodology supports reusable proofs of hardware components, provides for multiple implementations of the same specification, and allows both bottom up and top down verification styles. We provide mechanical assistance for our methodology in the Nuprl proof development system. Our method exploits Nuprl's rich type theory to encode the specification of a module in the type of the module. This allows us to elegantly describe parameterized hardware modules. The methodology is efficient because: the automated support reduces the amount of information that users must provide and the use of parameterized hardware modules eliminates redundant reasoning among proofs of hardware components. In this paper we explain our methodology and illustrate our approach with several examples of circuit verification.     

基于EHW的可进化传感器的研究

为克服常规传感器对信号采集和处理的局限,探求了一种具有智能传感并自适应于外部环境的机理,将常规传感器和可进化硬件相结合,提出了一种可进化传感器的基本框架,介绍了基于遗传算法和可进化硬件原理的具有自适应能力和容错特性的可进化传感器的初步研究。     

Quantum-inspired design of resilient substitution boxes: From coding to hardware implementation

S-boxes constitute a cornerstone component in symmetric-key cryptographic algorithms, such as DES and AES encryption systems. In block ciphers, they are typically used to obscure the relationship between the plaintext and the ciphertext. Non-linear and non-correlated S-boxes are the most secure against linear and differential cryptanalysis. In this paper, we focus on a twofold objective: first, we evolve regular S-boxes with high non-linearity and low auto-correlation properties; then automatically generate evolvable hardware for the obtained S-box. Targeting the former, we use a quantum-inspired evolutionary algorithm to optimize regularity, non-linearity and auto-correlation, which constitute the three main desired properties in resilient S-boxes. Pursuing the latter, we exploit the same algorithm to automatically generate the evolvable hardware designs of substitution boxes that minimize hardware space and encryption/decryption time, which form the two main hardware characteristics. We compare our results against existing and well-known designs, which were produced by using conventional methods as well as through genetic algorithm. We will show that our approach provides higher quality S-boxes coding as well as circuits.     

Debugging hardware designs using dynamic dependency graphs

Debugging is a time consuming task in hardware design. In this paper a new debugging approach based on the analysis of dynamic dependency graphs is presented. Powerful techniques for software debugging, including reverse debugging, dynamic forward and backward slicing, and spectrum-based fault localization are combined and adapted for hardware designs. A case study on designs with multiple faults approved the power of the proposed debugging methodology reducing the debugging time to 50% in comparison to conventional techniques.