SMW工法在丰田通商深基坑中的应用

SMW工法由于具有无渗漏水、造价低等优点,已得到越来越广泛的应用。本文以天津丰田通商工程SMW基坑围护施工为例,介绍了SMW工法的施工步骤及操作要点。     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

射频集成电路校准技术综述

射频集成电路(RFICs)对工艺偏差、器件失配、器件非线性等引入的静态非理想因素以及温度变化、增益改变、输入/输出频率变动等引入的动态非理想因素所表现出的鲁棒性较差。该文深入挖掘影响射频集成电路性能的关键因素，并对典型的校准算法进行归纳和总结，为高性能射频集成电路设计提供理论支撑。     

H.264/AVC整数DCT变换与量化的FPGA实现

根据H.264/AVC的变换量化原理,在FPGA上设计并实现了整数变换及量化部分。首先采用层次化、模块化的思想,将系统划分为多个功能模块,降低了硬件实现的复杂度,对DCT算法进行了优化,并对量化模块采用了流水线操作,最后设计全部采用Verilog硬件描述语言实现,并用Modelsim进行功能仿真,同时实验结果通过在Xilinx公司Vertex2P系列的XC2VP30 FPGA上验证。仿真及综合结果表明,与优化之前相比,系统所需时钟周期减少了29个,最大时钟频率可达到135.498MHz,为H.264标准的硬件实现提供了参考。     

应用于数字广播系统的高线性下变频器

An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 m CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 d B and a dynamic range of 10 d B. Measured noise figure is 8.2 d B, an IIP2 of 63 d Bm, an IIP3 of 17 d Bm at the minimum gain of 30 d B. The downconverter consumes about 7.7 m A under a supply of 1.2 V.     

一种宽范围高精度滤波器设计

提出了一种同时实现宽的带宽调谐范围和高的带宽频率精度的滤波器设计方法,克服了采用传统带宽校准方法设计滤波器时带宽调谐范围和精度相矛盾的弊端。设计方法通过计算机模拟验证和0.13μmCMOS工艺流片测试,结果与理论预期一致。实验结果表明,在实现5～30MHz的宽范围连续调谐的滤波器中,在保证带宽频率误差低于6%的情况下,滤波器仅需占用0.2mm2的面积。     

高灵敏度星载ADS-B信号解调算法

为提高星载自动相关广播监视系统(ADS-B)接收机的检测性能,研究了高灵敏度解调算法。利用基于匹配滤波的ADS-B信号帧头检测算法对信号准确定时和提取功率信息,该方法构建了特殊的帧头匹配脉冲序列,设计了信号控制状态机以确保在相关峰值最大处定位信号,并联合一部分数据位进行同步。利用多点加权振幅采样法提取比特信息和置信度。最后,采用基于置信度的纠错方法纠正校验错误的报文。板载验证表明,该解调算法能有效提升低信噪比条件下星载ADS-B信号的检测概率,最终接收机的灵敏度可达-95 dBm(数据包错误率5%)。     

背景可更新的动态目标跟踪系统设计

为了解决静态背景目标跟踪方法不适用于变化背景的问题,设计了背景可更新的动态目标跟踪系统;采用背景差值法提取运动目标,在FPGA片内实现背景更新控制、图像帧差、图像开操作、视频缓存与转换处理、运动参数译码等功能模块;设计中背景可实现手动刷新和定时自刷新两种更新方式,跟踪结果与监控视频以640*480分辨率、60Hz刷新频率在VGA显示器上同步显示,运动参数以400ms的刷新周期在VGA上定时刷新;实验结果表明,系统能实时、准确地跟踪运动目标。     

A continuously and widely tunable analog baseband chain with digital-assisted calibration for multi-standard DBS applications

This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/Hz^1/2.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.