A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

静态存储器保持状态下几种不同漏电流压制技术的漏电流拆分式分析

SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors.Generally,four kinds of techniques are often utilized for SRAM standby leakage reduction: V_dd lowering（VDDL）,V_ss rising（VSSR）,BL floating（BLF） and reversing body bias（RBB）.In this paper,we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage.It is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and temperature.This has been verified on a 65 nm SRAM test macro.     

Software Testing Applications Based on a Virtual Reality System

Software testing is an important part of software engineering and has been more and more popular as the rapid growth of the software products market. Good skills of communication with clients and programmers play a significant role for a tester during the test process. This paper presents some important and basic software testing applications （such as static testing, dynamic testing, black-box testing, white-box testing and their combinations） based on a virtual reality system, named as rocket digital simulation system （RDSS）. Different testing methods are exercised during the software developing lifecycle and finally achieving significant quality improvement.     

The design of VMEbus bridge controller with SHARC bus

Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit （IC）, this paper presents a scheme of adopting CPLD/FPGA （Complicated Programmable Logic Device/Field Programmable Gate Array） to design bridge controller between VMEbus and local bus. SHARC DSP （Digital Signal Processor） bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA （Direct Memory Access） controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.     

一种用于UHF RFID标签的超低功耗数字处理机设计

A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.     

AN IMPROVED ALL ZERO BLOCK FINDING METHOD BASED ON THE STATISTIC CHARACTERISTICS OF DCT TRANSFORM COEFFICIENTS

In the H.263 video codec related systems, motion estimation and Discrete Cosine Transform （DCT） have the most computational requirements. In order to reduce complexity of the encoder to dedicate more resources to other functions, according to the study of existing methods, an Improved All Zero Block Finding （IAZBF） method based on the statistic characteristics of DCT coefficients is proposed. Compared with existing methods, IAZBF improves the detecting efficiency by about 50% without importing too much extra computation requirement. Being computed with additions and shifts instead of complicated multiplications, IAZBF is of low computation complexity, especially for low-end processors. In addition, IAZBF upholds picture fidelity and remains compatible with the H.263 bitstream standard.     

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.     

Design and optimization for multiprocessor interactive GPU

In order to achieve maximization of parallelism, effective distribution of rendering tasks, balance between performance and flexibility in graphics processing pipeline, this article presents design, performance analysis and optimization for multi-core interactive graphics processing unit （MIGPU）. This processor integrates twelve processing cores with specific instruction set architecture and many sophisticated application-specific accelerators into a 3D graphics engine. It is implemented on XC6VLX550T field programmable gate array （FPGA）. MIGPU supports OpenGL2.0 with programmable front-end processor, vertex shader, plane clipper, geometry transformer, three-D clippers and pixel shaders. For boosting the performance of MIGPU, the relationship model is established between primitive types, vertices, pixels, and the effect of culling, clipping, and memory access, and shows a way to improve the speed up of the graphics pipeline. It is capable of assigning graphics rendering tasks to different processors for efficiency and flexibility. The pixel filling rate can reach to 40 Mpixel/s at its peak performance.     

An improved adaptive threshold modulation method for jitter reduction in SDH/SONET

Adaptive threshold modulation is widely adopted in SDH/SONET network for pointer processing and mapping. When the processing rate is very high, the performance of an all digital implementation is limited by the phase error resolution. Phase error re-sampling technique is adopted here for the all digital implementation of an improved adaptive threshold modulation, which can work in greatly reduced operating speed with high jitter and wander performance. The improved method is adopted in AU-4 and TU-12 pointer processors and the simulated performance is given.     

On-Chip Reconfigurable Microwave Photonic Processor

Microwave photonic processors leverage the modern photonics technique to process the microwave signal in the optical domain, featuring high speed and broad bandwidth. Based on discrete optical and microwave components, different microwave photonic processors are reported. Due to the limitation of the optoelectronic components, most of the realized processors are designed to serve a specific demand. With the booming development of photonic integrated circuits(PICs), new possibilities are opened f...     

Optical Constants and Structure of ZnO Films by Radio Frequency Magnetron Sputtering

ZnO films are deposited on glass slides by radio frequency（RF） magnetron sputtering under different powers. The polycrystal structures and surface morphologies of the film are investigated. The optical transmission spectra for the ZnO films are measured within the range from 300 nm to 800 nm. The optical constants and thickness of the films are determined using a nonlinear programming method suggested by Birgin et al. The band gap of the film increases with reducing the nano-size of the film grains. The packing density of the films can be improved by reducing the RF power.     

A Versatile High-speed Image Processing System Based on DSP and CPLD

In this paper, we present an optimized design method for high-speed embedded image processing system using 32 bit floating-point Digital Signal Processor （DSP） and Complex Programmable Logic Device （CPLD）. The DSP acts as the main processor of the system： executes digital image processing algorithms and operates other devices such as image sensor and CPLD. The CPLD is used to acquire images and achieve complex logic control of the whole system. Some key technologies are introduced to enhance the performance of our system. In particular, the use of DSP/BIOS tool to develop DSP applications makes our program run much more efficiently. As a result, this system can provide an excellent computing platform not only for executing complex image processing algorithms, but also for other digital signal processing or multi-channel data collection by choosing different sensors or Analog-to-Digital （A/D） converters.     

Design and Implementation of a Cueing Wideband Digital EW Receiver

A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.     

Analysis of Cell-averaging Based Detectors for χ2 Fluctuating Targets in Multitarget Environments

The χ^2 family of signal fluctuation distributions represents the main fluctuation models which most radar targets follow it in their reflections. This family can be categorized as fluctuation distribution with two degrees of freedom and those with four degrees of freedom. The first category represents all important class of fluctuation models which when illuminated by a coherent pulse train, return a train of fully correlated pulses （Swerling Ⅰ model） or fully decorrelated pulses （Swerling Ⅱ model）. The detection of this type of fluctuating targets is therefore of great importance. This paper is devoted to the analysis of Cell-Averaging （CA） based detectors for the case where the radar receiver noncoherently integrates M square-law detected pulses and the signal fluctuation obeys 2 statistics with two degrees of freedom. These detectors include the Mean-Of （MO）, the Greatest-Of （GO） and the Smallest-Of（SO） schemes. In these processors, the estimation of the noise power levels from the leading and the trailing reference windows is based on the CA technique. Exact formulas for the detection probabilities are derived, in the absence as well as in the presence of spurious targets. The primary and the secondary interfering targets are assumed to be fluctuating in accordance with the χ^2 fluctuation model with two degrees of freedom （SWI ＆ SWII）. The numerical results show that the MO version has the best homogeneous performance, the SO scheme has the best multiple-target performance, while the GO procedure does not offer any merits, neither in the absence nor in the presence of outlying targets.     

He—Ne激光穿透动物组织深度的实验

For more efficient use of low power He.Ne laser in clinical truatme.at the dbpth of its peuolration in animal and human tisue was measured by both photo-electric（reported cleswhere）and photogrephic record.It was found that photographic effect could ba obtninod in the human tissue through the skin to a depth of aroun 27 mm within 10-15 minutes radia tion.The ponetrance of pork fat was the highest（117mm）followed by rabbit muscle（100mm）and lean pork（84mm）/The dog and humsn muscle tissues werc more resistant to penetrate being 20mm for dog meat 15mm for dog skin and 34mm for human tissue through the skin,Since higher expo;sure effect was obtained by prologning the time of exposure the time of radiation is an important factor in clinical treatment with He-Ne laser.     

Digital Signal Processing for Optical Access Networks

In this paper, we investigate advanced digital signal process ing （DSP） at the transmitter and receiver side for signal pre equalization and postequalization in order to improve spec trum efficiency （SE） and transmission distance in an optical access network. A novel DSP scheme for this optical super Nyquist filtering 9 Quadrature Amplitude Modulation （9 QAM） like signals based on muhimodulus equalization with out post filtering is proposed. This scheme recovers the Ny quist filtered Quadrature PhaseShift Keying （QPSK） signal to a 9QAMlike one. With this technique, SE can be increased to 4 b/s/Hz for QPSK signals. A novel digital superNyquist signal generation scheme is also proposed to further suppress the Nyquist signal bandwidth and reduce channel crosstalk without the need for optical prefiltering. Only optical cou plers are needed for superNyquist wavelengthdivisionmulti plexing （WDM） channel multiplexing. We extend the DSP for shorthaul optical transmission networks by using highorder QAMs. We propose a highspeed Can＇ierless Amplitude/Phase 64 QAM （CAP64 QAM） system using directly modulated la ser （DML） based on direct detection and digital equalization. Decisiondirected least mean square is used to equalize the CAP64QAM. Using this scheme, we generate and transmit up to 60 Gbit/s CAP64QAM over 20 km standard single mode fiber based on the DML and direct detection. Finally, several key problems are solved for real time orthogonalfre quencydivisionmultiplexing （OFDM） signal transmission aml processing. With coherent detection, up to 100 Glfit/s 16 QAMOFDM realtime transmission is possible.     

Multi-digital Still Cameras with CCD

Digital still camera is a completely typical tool for capturing the digital images. With the development of IC technology and optimization-algorithm, the performance of digital still cameras（DSCs） will be more and more powerful in the world. But can we obtain the more and better info using the combined information from the multi-digital still camera？ The answer is yes by some experiments. By using multi-DSC at different angles, the various 3-D informations of the object are obtained.     

Parallel Processing Design for LTE PUSCH Demodulation and Decoding Based on Multi-Core Processor

The Long Term Evolution (LTE) system imposes high requirements for dispatching delay.Moreover,very large air interface rate of LTE requires good processing capability for the devices processing the baseband signals.Consequently,the single-core processor cannot meet the requirements of LTE system.This paper analyzes how to use multi-core processors to achieve parallel processing of uplink demodulation and decoding in LTE systems and designs an approach to parallel processing.The test results prove that this approach works quite well.     

Acousto—optic Devices：Theory and Application

The basics and applications of acousto-optic devices are described,The applications include acousto-optic spectrum analyzer,acousto-optic deflector,acousto-optic processors and acousto-optic digital matrix computer.     

一种无线宽带收发机载波泄漏校准和补偿技术

A carrier leakage calibration and compensation technique based on digital baseband for a wideband wireless communication transceiver is proposed. The digital baseband transmits a calibration signal, samples the signal which passes through the transmitter path and the calibration loop in the RF chip, measures the carrier leakage by analyzing the sampled data and compensates it. Compared with a self-calibration technique in the RF chip, the proposed technique saves area and power consumption for the wireless local area network （WLAN） solution. This technique has been successfully used for 802.1 In system and satisfies the requirement of the standard by achieving over 50 dB carrier leakage suppression.