Asymmetrical Quantum Encryption Protocol Based on Quantum Search Algorithm

Quantum cryptography and quantum search algorithm are considered as two important research topics in quantum information science. An asymmetrical quantum encryption protocol based on the properties of quantum one-way function and quantum search algorithm is proposed. Depending on the no-cloning theorem and trapdoor one-way functions of the public- key, the eavesdropper cannot extract any private-information from the public-keys and the ciphertext. Introducing key-generation randomized logarithm to improve security of our proposed protocol, i.e., one private- key corresponds to an exponential number of public-keys. Using unitary operations and the single photon measurement, secret messages can be directly sent from the sender to the receiver. The security of the proposed protocol is proved that it is informationtheoretically secure. Furthermore, compared the symmetrical Quantum key distribution, the proposed protocol is not only efficient to reduce additional communication, but also easier to carry out in practice, because no entangled photons and complex operations are required.     

SOI基蓝紫光敏感光电探测器的设计与模拟

According to Lambert’s law,a novel structure of photodetectors,namely photodetectors in siliconon-insulator,is proposed.By choosing a certain thickness value for the SOI layer,the photodetector can absorb blue/violet light effectively and affect the responsivity of the long wavelength in the visible and near-infrared region,making a blue/violet filter unnecessary.The material of the SOI layer is high-resistivity floating-zone silicon which can cause the neutral N type SOI layer to become fully depleted after doping with a P type impurity.This can improve the collection efficiency of short-wavelength photogenerated carriers.The device structure was optimized through numerical simulation,and the results show that the photodiode is a kind of high performance photodetector in the blue/violet region.     

高性能的电吸收调制器

A 100-μm-long electroabsorption modulator monolithically integrated with passive waveguides at the input and output ports is fabricated through ion implantation induced quantum well intermixing, using only a twostep low-pressure metal-organic vapor phase epitaxial process. An InGaAsP/InGaAsP intra-step quantum well is introduced to the active region to improve the modulation properties. In the experiment high modulation speed and high extinction ratio are obtained simultaneously, the electrical-to-optical frequency response （E/O response） without any load termination reaches to 22 GHz, and extinction ration is as high as 16 dB.     

Single-mode GaAs/AIGaAs quantum cascade microlasers

Single-mode edge emitting GaAs/AlGaAs quantum cascade microlasers at a wavelength of about 11.4μm were realized by shortening the Fabry-Perot cavity length. The spacing of the longitudinal resonator modes is inversely proportional to the cavity length. Stable single-mode emission with a side mode suppression ratio of about 19 dB at 85 K for a 150-μm-long device was demonstrated.     

倾斜腔结构对量子点光有源器件性能的影响

Quantum-dot laser diodes （QD-LDs） with a Fabry-Perot cavity and quantum-dot semiconductor optical amplifiers （QD-SOAs） with 7° tilted cavity were fabricated. The infuence of a tilted cavity on optoelectronic active devices was also investigated. For the QD-LD, high performance was observed at room temperature. The threshold current was below 30 mA and the slope efficiency was 0.36 W/A. In contrast, the threshold current of the QDSOA approached 1000 mA, which indicated that low facet reflectivity was obtained due to the tilted cavity design. A much more inverted carrier population was found in the QD-SOA active region at high operating current, thus offering a large optical gain and preserving the advantages of quantum dots in optical amplification and processing applications. Due to the inhomogeneity and excited state transition of quantum dots, the full width at half maximum of the electroluminescence spectrum of the QD-SOA was 81.6 nm at the injection current of 120 mA, which was ideal for broad bandwidth application in a wavelength division multiplexing system. In addition, there was more than one lasing peak in the lasing spectra of both devices and the separation of these peak positions was 6-8 nm, which is approximately equal to the homogeneous broadening of quantum dots.     

Shallow impurity states in Alx Gam_xAs cylindrical quantum wire

Polarons bound to a shallow Coulomb impurity center in cylindrical quantum wire is studied by a vari- ational approach. The binding energies of the shallow impurity states in AlxGal-xAs cylindrical quantum wire are calculated as functions of the composition x and the impurity position. It is confirmed that the binding energies are reduced obviously by the influence of the electron-phonon interaction and the binding energies are increased with increasing the composition x.     

Performance of an Improved One-Way Error Reconciliation Protocol Based on Key Redistribution

In data post-processing for quantum key distribution, it is essential to have a highly efficient error reconciliation protocol. Based on the key redistribution scheme, we analyze a one-way error reconciliation protocol by data simulation. The relationship between the error correction capability and the key generation efficiency of three kinds of Hamming code are demonstrated. The simulation results indicate that when the initial error rates are （0,1.5%], （1.5,4%], and （4,11%], using the Hamming （31,26）, （15,11）, and （7,4） codes to correct the error, respectively, the key generation rate will be maximized. Based on this, we propose a modified one-way error reconciliation protocol which employs a mixed Hamming code concatenation scheme. The error correction capability and key generation rate are verified through data simulation. Using the parameters of the posterior distribution based on the tested data, a simple method for estimating the bit error rate （BER） with a given confidence interval is estimated. The simulation results show that when the initial bit error rate is 10.00%, after 7 rounds of error correction, the error bits are eliminated completely, and the key generation rate is 10.36%; the BER expectation is 2.96×10^-10, and when the confidence is 95% the corresponding BER upper limit is 2.17×10^-9. By comparison, for the single （7,4） Hamming code error reconciliation scheme at a confidence of 95%,the key generation rate is only 6.09%, while the BER expectation is 5.92x 10＂9, with a BER upper limit of 4.34×10^-8. Hence, our improved protocol is much better than the original one.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

SDN-Based Data Offioading for 5G Mobile Networks

The rapid growth of 3G/4G enabled devices such as smartphones and tablets in large numbers has created increased demand formobile data services.Wi-Fi offloading helps satisfy the requirements of data-rich applications and terminals with improved multi-media.Wi-Fi is an essential approach to alleviating mobile data traffic load on a cellular network because it provides extra capaci-ty and improves overall performance.In this paper,we propose an integrated LTE/Wi-Fi architecture with software-defined net-working(SDN)abstraction in mobile backhaul and enhanced components that facilitate the move towards next-generation 5G mo-bile networks.Our proposed architecture enables programmable offloading policies that take into account real-time network condi-tions as well as the status of devices and applications.This mechanism improves overall network performance by deriving real-time policies and steering traffic between cellular and Wi-Fi networks more efficiently.     

应力和电阻率可控的适用于高品质因子MEMS器件的原位掺硼LPCVD多晶硅薄膜

The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition （LPCVD） are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600-800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems （MEMS） devices, especially in high resonance frequency （high-f） and high quality factor （high-Q） MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2-5 mΩ·cm. These reported approaches avoid the high temperature annealing process （〉 1000 ℃）, and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.     

Survivable Virtual Network Mapping Using Optimal Backup Topology in Virtualized SDN

Software-Defined Network architecture offers network virtualization through a hypervisor plane to share the same physical substrate among multiple virtual networks. However, for this hypervisor plane, how to map a virtual network to the physical substrate while guaranteeing the survivability in the event of failures, is extremely important. In this paper, we present an efficient virtual network mapping approach using optimal backup topology to survive a single link failure with less resource consumption. Firstly, according to whether the path splitting is supported by virtual networks, we propose the OBT-I and OBT-II algorithms respectively to generate an optimal backup topology which minimizes the total amount of bandwidth constraints. Secondly, we propose a Virtual Network Mapping algorithm with coordinated Primary and Backup Topology （VNM-PBT） to make the best of the substrate network resource. The simulation experiments show that our proposed approach can reduce the average resource consumption and execution time cost, while improving the request acceptance ratio of VNs.     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

应用于低中频和零中频DVB调谐器中8阶信道滤波器设计

An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves -52 dB and the out-band IM3 achieves -55 dB with -11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18μm CMOS process, consumes 4 mA current with 1.8 V power supply.     

Distributed Power Control for Energy Conservation in Hybrid Cellular Network with Device-to-Device Communication

Device-to-Device （D2D） com- munication has been proposed as a promising implementation of green communication to benefit the existed cellular network. In order to limit cross-tier interference while explore the gain of short-range communication, we devise a series of distributed power control （DPC） schemes for energy conservation （EC） and enhancement of radio resource utilization in the hybrid system. Firstly, a constrained opportunistic power control model is built up to take advantage of the interference avoidance methodology in the presence of service requirement and power constraint. Then, biasing scheme and admission control are added to evade ineffective power consumption and maintain the feasibility of the system. Upon feasibility, a non-cooperative game is further formulated to exploit the profit in EC with minor influence on spectral efficiency （SE）. The convergence of the DPC schemes is validated and their performance is confirmed via simulation results.     

Large-signal characterizations of DDR IMPATT devices based on group Ⅲ-Ⅴ semiconductors at millimeter-wave and terahertz frequencies

Large-signal （L-S） characterizations of double-drift region （DDR） impact avalanche transit time （IM- PATT） devices based on group III-V semiconductors such as wurtzite （Wz） GaN, GaAs and InP have been carried out at both millimeter-wave （mm-wave） and terahertz （THz） frequency bands. A L-S simulation technique based on a non-sinusoidal voltage excitation （NSVE） model developed by the authors has been used to obtain the high frequency properties of the above mentioned devices. The effect of band-to-band tunneling on the L-S properties of the device at different mm-wave and THz frequencies are also investigated. Similar studies are also carried out for DDR IMPATTs based on the most popular semiconductor material, i.e. Si, for the sake of comparison. A compara- tive study of the devices based on conventional semiconductor materials （i.e. GaAs, InP and Si） with those based on Wz-GaN shows significantly better performance capabilities of the latter at both mm-wave and THz frequencies.     

具有频率调谐的GNSS接收机双模复数滤波器

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18μm CMOS process.This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz.A fully differential OTA with source degeneration is used to provide sufficient linearity.Furthermore,a ring CCO based frequency tuning scheme is proposed to reduce frequency variation.The measured results show that in narrow-band mode the image rejection ratio（IMRR）is 35 dB,the filter dissipates 0.8 mA from the 1.8 V power supply,and the out-of-band rejection is 50 dB at 6 MHz offset.In wide-band mode,IMRR is 28 dB and the filter dissipates 3.2 mA.The frequency tuning error is less than±2%.     

适用于双金属栅集成的TaN湿法腐蚀

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

基于非线性DAC的高速直接数字频率合成器

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.     

掉电后SRAM防数据残留物理攻击的安全策略

This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered- off static random access memory （SRAM）. Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.