基于分治策略的加法器测试向量生成技术

为应对数据通道测试中向量生成计算复杂度的日益增长,针对加法器进行研究,提出了一种基于分治策略的加法器测试向量生成技术。首先将被测加法器电路分解为并发模块和顺序模块,分别生成对应这些模块故障全覆盖的测试向量子集,再将他们的输入信号映射为被测加法器电路的基本输入,经去除冗余向量后得到完整的测试向量集。给出的实验结果表明了该技术能有效地降低加法器测试向量生成的计算量,特别对于大规模加法器电路的测试生成,其效果更佳。

Divide and conquer strategy based test vector generation technology for adders

To cope with the increasingly computation complexity of test vector generation for the datapath in large-scale digital integrated circuits, a new test vector generation technology is proposed on the basis of divide-and-conquer strategy, according to the research on the structures of adders. The circuit-under-test is firstly divided into parallel blocks and serial blocks. The full fault coverage test vector subset is generated for each block. By mapping the pseudo-inputs to the primary inputs, the test vectors in the subsets are converted to the test vectors for the original circuit-under-test. Then, the redundant vectors are removed, to form the final test vector set for 100% fault coverage. The experiment results demonstrate that the proposed technology can efficiently reduce the computation complexity of test vector generation. The effect of complexity reduction is more impressive when it is applied to large-scale adders.