欧姆接触金属退火对应力AlGaN/GaN异质结构中电子迁移率的影响

The influence of annealed ohmic contact metals on the electron mobility of a two dimensional electron gas （2DEG） is investigated on ungated AlGaN/GaN heterostructures and AlGaN/GaN heterostructure field effect transistors （AlGaN/GaN HFETs）. Current-voltage （I-V） characteristics for ungated AlGaN/GaN heterostructures and capacitance-voltage （C-V） characteristics for AlGaN/GaN HFETs are obtained, and the electron mobility for the ungated AlGaN/GaN heterostructure is calculated. It is found that the electron mobility of the 2DEG for the ungated AlGaN/GaN heterostructure is decreased by more than 50% compared with the electron mobility of Hall measurements. We propose that defects are introduced into the AlGaN barrier layer and the strain of the AlGaN barrier layer is changed during the annealing process of the source and drain, causing the decrease in the electron mobility.     

SDN-Based Data Offioading for 5G Mobile Networks

The rapid growth of 3G/4G enabled devices such as smartphones and tablets in large numbers has created increased demand formobile data services.Wi-Fi offloading helps satisfy the requirements of data-rich applications and terminals with improved multi-media.Wi-Fi is an essential approach to alleviating mobile data traffic load on a cellular network because it provides extra capaci-ty and improves overall performance.In this paper,we propose an integrated LTE/Wi-Fi architecture with software-defined net-working(SDN)abstraction in mobile backhaul and enhanced components that facilitate the move towards next-generation 5G mo-bile networks.Our proposed architecture enables programmable offloading policies that take into account real-time network condi-tions as well as the status of devices and applications.This mechanism improves overall network performance by deriving real-time policies and steering traffic between cellular and Wi-Fi networks more efficiently.     

Design of a 16 gray scales 320×240 pixels OLED-on-silicon driving circuit

A 320×240 pixel organic-light-emitfing-diode-on-silicon （OLEDoS） driving circuit is implemented using the standard 0.5μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three- transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit＇s power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4 × 28.4μm^2 and the display area is 10.7 × 8.0 mm^2 （the diagonal is about 13 mm）. The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.     

γ-LiAlO2衬底上m面GaN薄膜的各向异性的测试和分析

A 0.09 mm m-plane GaN film is deposited via hydride vapor phase epitaxy （HVPE） on a γ-LiAlO2 substrate. To research the anisotropy between directions with different angles with the c-axis in the m plane, photoluminescence （PL） measurements were carried out. The results show that the electronic transition was influenced by the electric field along the c-axis, which results in an obvious anisotropy, but the influence was weakened by the hexagonal symmetry along the c-axis.     

Sheet carrier density dependent Rashba spin splitting in the Alo.sGao.sN/GaN/ Alo.sGao.sN quantum well＊

The Rashba coefficient and Rashba spin splitting for the first subband of the Alo.5Gao.5N/GaN/ Alo.5Gao.5N quantum well （QW） with various sheet carrier densities （Ns） are calculated by solving Schr6dinger and Poisson equations self-consistently. The Rashba spin splitting for the first subband at the Fermi level is considerable and increases evidently with Ns, since the Rashba coefficient, especially the Fermi wave vector increase rapidly. With increasing Ns, the peak of the wave function for the first subband moves towards the left heterointerface, and the average electric field in the well increases, so the two dominant contributions coming from the well and the heterointerface increase. Therefore, the strong polarization electric field and high density of 2DEG in III-nitrides heterostructures are of great importance to a and make the Rashba spin splitting in A1GaN/GaN QWs comparable to that of narrow-gap III-V materials. The results indicate that the sheet carrier density is an important parameter affecting the Rashba coefficient and Rashba spin splitting in A1GaN/GaN QWs, showing the possible application of this material system in spintronic devices.     

Design and Implementation of An Active Multibeam Antenna System with 64 RF Channels and 256 Antenna Elements for Massive MIMO Application in 5G Wireless Communications

This paper focuses on the design and implementation of an active multibeam antenna system for massive MIMO applications in 5G wireless communications. The highly integrated active multibeam antenna system is designed and implemented at 5.8 GHz with 64 RF Channels and 256 antenna elements. The 64-channel highly integrated active multibeam antenna system provides a verification platform for digital beamforming algorithm and massive MIMO channel estimation for next generation wireless communications.     

双外延基区BJT基区渡越时间的模型研究

The doping profile function of a double base epilayer is constructed according to drift-diffusion theory. Then an analytical model for the base transit time τb is developed assuming a small-level injection based on the characteristics of the 4H-SiC material and the principle of the 4H-SiC BJTs. The device is numerically simulated and validated based on two-dimensional simulation models. The results show that the built-in electric field generated by the double base epilayer configuration can accelerate the carriers when transiting the base region and reduce the base transit time. From the simulation results, the base transit time reaches a minimal value when the ratio of L2/L1 is about 2.     

An 11 mW 79 dB DR △Σ modulator for ADSL applications

This paper shows the design of a second-order multi-bit△Σmodulator with hybrid structure for ADSL applications.A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12%of the time from PH1,which relaxes the speed of OTAs,comparators and the DEM block.The clock feed through problem of the passive adder is solved by revising the timing of the comparators and the adder.The chip is designed and fabricated in UMC 0.18μm CMOS technology.Measurement results show that with an oversampling ratio of 32 and a clock rate of 80 MHz,the modulator can achieve 79 dB dynamic range,71.3 dB SNDR,11 mW power consumption from a 1.8 V power supply.The FOM is 1.47 pJ/step.     

利用三氯氢硅(TCS)作为硅源在4H-SiC上外延生长的研究

Epitaxial growth on n-type 4H-SiC 8° off-oriented substrates with a size of 10 × 10 mm^2 at different temperatures with various gas flow rates has been performed in a horizontal hot wall CVD reactor, using trichlorosilane （TCS） as a silicon precursor source together with ethylene as a carbon precursor source. The growth rate reached 23 μm/h and the optimal epilayer was obtained at 1600℃ with a TCS flow rate of 12 sccm in C/Si of 0.42, which has a good surface morphology with a low RMS of 0.64 nm in an area of 10 x 10 pm2. The homoepitaxial layer was obtained at 1500℃ with low growth rate （〈 5 μm/h） and the 3C-SiC epilayers were obtained at 1650 ℃ with a growth rate of 60-70 μm/h. It is estimated that the structural properties of the epilayers have a relationship with the growth temperature and growth rate. Silicon droplets with different sizes are observed on the surface of the homoepitaxial layer in a low C/Si ratio of 0.32.     

槽栅MOSHEMT研制与特性分析

An A1GaN/GaN recessed-gate MOSHEMT was fabricated on a sapphire substrate. The device, which has a gate length of 1μm and a source-drain distance of 4μm, exhibits a maximum drain current density of 684mA/mrn at Vgs = 4V with an extrinsic transconductance of 219 mS/mm. This is 24.3% higher than the transconductance of conventional A1GaN/GaN HEMTs. The cut-off frequency and the maximum frequency of oscillation are 9.2 GHz and 14.1 GHz, respectively. Furthermore, the gate leakage current is two orders of magnitude lower than for the conventional Schottky contact device.     

The Bipolar Field-Effect Transistor:XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

This paper reports the physical realization of the Bipolar Field-Effect Transistor （BiFET） and its onetransistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor （the bulk transistor） and the impurethin-base Silicon-on-Insulator （SOI） transistor and the two-MOS-gates on thin base transistors （the FinFET and the Thin Film Transistor TFF）. Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.     

应用于65nm CMOS技术节点漏电流分析的精确快速的查表模型

Novel physical models for leakage current analysis in 65 nm technology are proposed. Taking into consideration the process variations and emerging effects in nano-scaled technology, the presented models are capable of accurately estimating the subthreshold leakage current and junction tunneling leakage current in 65 nm technology. Based on the physical models, new table look-up models are developed and first applied to leakage current analysis in pursuit of higher simulation speed. Simulation results show that the novel physical models are in excellent agreement with the data measured from the foundry in the 65 nm process, and the proposed table look-up models can provide great computational efficiency by using suitable interpolation techniques. Compared with the traditional physical-based models, the table look-up models can achieve 2.5X speedup on average on a variety of industry circuits.     

一种新型4G通信室内覆盖方案

根据4G通信室内覆盖方案的工作频率特性及覆盖要求,研究制造出了具有较宽工作频率的新型室内漏泄电缆天线。该新型漏泄电缆天线主要由连接器、1／2”小规格漏缆和负载组装而成。文中对基于该漏泄电缆天线的4G室内覆盖新方案进行了研究,对4G通信室内覆盖新方案和传统天线覆盖方案的性能及成本进行了对比分析,最后举例对该覆盖新方案的具体设计方式进行了说明。     

硅基二维通道电子倍增器微孔阵列基体形成的光电化学技术研究

A semiconductor PEC etching method is applied to fabricate the n-type silicon deep micropore channel array. In this method, it is important to arrange the direction of the micropore array along the crystal orientation of the Si substrate. Otherwise, serious lateral erosion will happen. The etching process is also relative to the light intensity and HF concentration. 5% HF concentration and 10-15 cm distance between the light source and the silicon wafer are demonstrated to be the best in our experiments. The n-type silicon deep micropore channel array with aperture of 3/2m and aspect ratio of 40-60, whose inner walls are smooth, is finally obtained.     

具有缓冲层和N型埋层的高压兼容Bi-CMOS工艺的超结LDMOS

A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.     

Breakdown voltage and current collapse of F-plasma treated AIGaN/GaN HEMTs

The breakdown and the current collapse characteristics of high electron mobility transistors （HEMTs） with a low power F-plasma treatment process are investigated. With the increase of F-plasma treatment time, the saturation current decreases, and the threshold voltage shifts to the positive slightly. Through analysis of the Schottky characteristics of the devices with different F-plasma treatment times, it was found that an optimal F-plasma treatment time of 120 s obviously reduced the gate reverse leakage current and improved the breakdown voltage of the devices, but longer F-plasma treatment time than 120 s did not reduce gate reverse leakage current due to plasma damage. The current collapse characteristics of the HEMTs with F-plasma treatment were evaluated by dual pulse measurement at different bias voltages and no obvious deterioration of current collapse were found after low power F-plasma treatment.     

The Bipolar Field-Effect Transistor: VII. The Unipolar Current Mode for Analog-RF Operation (Two-MOS-Gates on Pure-Base)

This paper reports the DC steady-state current-voltage and conductance-voltage characteristics of a Bipolar Field-Effect Transistor （BiFET） under the unipolar （electron） current mode of operation, with bipolar （electron and hole） charge distributions considered. The model BiFET example presented has two MOS-gates on the two surfaces of a thin pure silicon base layer with electron and hole contacts on both edges of the thin base. The hole contacts on both edges of the thin pure base layer are grounded to give zero hole current. This 1-transistor analog-RF Basic Building Block nMOS amplifier circuit, operated in the unipolar current mode, complements the 1-transistor digital Basic Build Block CMOS voltage inverter circuit, operated in the bipolar-current mode just presented by us.     

Large-signal characterizations of DDR IMPATT devices based on group Ⅲ-Ⅴ semiconductors at millimeter-wave and terahertz frequencies

Large-signal （L-S） characterizations of double-drift region （DDR） impact avalanche transit time （IM- PATT） devices based on group III-V semiconductors such as wurtzite （Wz） GaN, GaAs and InP have been carried out at both millimeter-wave （mm-wave） and terahertz （THz） frequency bands. A L-S simulation technique based on a non-sinusoidal voltage excitation （NSVE） model developed by the authors has been used to obtain the high frequency properties of the above mentioned devices. The effect of band-to-band tunneling on the L-S properties of the device at different mm-wave and THz frequencies are also investigated. Similar studies are also carried out for DDR IMPATTs based on the most popular semiconductor material, i.e. Si, for the sake of comparison. A compara- tive study of the devices based on conventional semiconductor materials （i.e. GaAs, InP and Si） with those based on Wz-GaN shows significantly better performance capabilities of the latter at both mm-wave and THz frequencies.     

Analysis of AIGaN/GaN high electron mobility transistors failure mechanism under semi-on DC stress

Semi-on DC stress experiments were conducted on A1GaN/GaN high electron mobility transistors （HEMTs） to find the degradation mechanisms during stress. A positive shift in threshold voltage （VT） and an increase in drain series resistance （RD） were observed after semi-on DC stress on the tested HEMTs. It was found that there exists a close correlation between the degree of drain current degradation and the variation in VT and RD. Our analysis shows that the variation in Vx is the main factor leading to the degradation of saturation drain current （IDs）, while the increase in RD results in the initial degradation of Ios in linear region in the initial several hours stress time and then the degradation of VT plays more important role. Based on brief analysis, the electron trapping effect induced by gate leakage and the hot electron effect are ascribed to the degradation of drain current during semi-on DC stress. We suggest that electrons in the gate current captured by the traps in the A1GaN layer under the gate metal result in the positive shift in VT and the trapping effect in the gate-drain access region induced by the hot electron effect accounts for the increase in RD.     

基于一种可靠非均匀场限环终端结构的1.4kV 4H型碳化硅PiN二极管

This paper presents the design and fabrication of an effective, robust and process-tolerant floating guard ring termination on high voltage 4H-SiC PiN diodes. Different design factors were studied by numerical simulations and evaluated by device fabrication and measurement. The device fabrication was based on a 12 μm thick drift layer with an N-type doping concentration of 8 × 10^15 cm^-3. P^＋ regions in the termination structure and anode layer were formed by multiple aluminum implantations. The fabricated devices present a highest breakdown voltage of 1.4 kV, which is higher than the simulated value. For the fabricated 15 diodes in one chip, all of them exceeded the breakdown voltage of 1 kV and six of them reached the desired breakdown value of 1.2 kV.