镶嵌在超薄SiO2层中的纳米硅的库仑阻塞现象

采用等离子体氧化和逐层(layer by layer)生长技术在等离子体增强化学气相沉积 (PECVD)系统中原位制备了SiO2/nc-Si/SiO2的双势垒纳米结构,从nc-Si薄膜的喇曼谱中观察到结晶峰,估算出该薄膜的晶化成分和平均晶粒尺寸分别约为65%和6nm.通过对该纳米结构的电容-电压(C-V)测量,研究了载流子的隧穿和库仑阻塞特性.在不同测试频率的C-V谱中观测到了由于载流子隧穿引起的最大电容值抬升现象.通过低温低频C-V谱,计算出该结构中nc-Si的库仑荷电能为57meV.     

等离子体氧化制备超薄SiO_2层的性质

利用等离子体氧化方法在单晶硅片上制备了厚度小于 10 nm的超薄 Si O2 层 .通过傅里叶红外光谱 (FTIR)、X射线光电子谱 (XPS)、透射电子显微镜 (TEM)、椭圆偏振法和电流电压 (I- V)、电容电压 (C- V)测量对生成的超薄氧化层性质进行研究     

纳米硅异质结二极管

在 p型单晶硅衬底上沉积一层掺磷 N+ 型纳米硅薄膜 ,形成 nc- Si∶ H/ c- Si构成的 N+ / p异质结构。文中报道了它的独特性能 :其反向击穿电压可达 75V,反向漏电流仅 n A量级 ,反向开关时间为 1.5ns,可望应用于微波波段。由其 I- V及 C- V特性初步分析了结的性质及电输运机制。     

MFIS结构的C-V特性

研究了运用SOL-GEL方法制备的Au/PZT(铅锆钛)/ZrO2/Si结构电容即 MFIS(Metal/Ferroelectric /Insulator/Semiconductor)电容的方法,并对其进行了SEM、C- V特性测试及ZrO2介质层介电常数分析 .研究了C-V存储窗口(Memory Window)电压与铁电薄膜和介质层厚度比的关系,得出MFIS电容结构中最佳铁电薄膜和介质层厚度比为7～10左右 ,在外加电压-5V～+5V时存储窗口可达2.52 V左右 .     

SiC/nc-Si多层薄膜的光致可见发光谱的紧束缚理论

用Vogl提出的sp3s*紧束缚模型来研究碳化硅/纳米硅(SiC/nc-Si)多层薄膜的能带结构与其光致发光谱的关系,并设计出SiC/nc-Si多层薄膜最佳结构为{Si}1{SiC}8,即碳化硅层的厚度是纳米硅层厚度的8倍时的超晶格结构蓝光发射的效率最高.在等离子体增强化学气相沉积系统中,通过控制进入反应室的气体种类逐层沉积含氢非晶SiCx:H(a-SiCx:H)和非晶Si:H(a-Si:H)薄膜,然后经过高温热退火处理,成功制备出了晶化纳米SiC/nc-Si(多晶SiC和纳米Si)多层薄膜.利用截面透射电子显微镜技术分析了a-SiCx:H/nc-Si:H多层薄膜的结构特性,表明制得的超晶格结构稍微偏离设计,它的结构为{Si}1{SiC}5.最后对晶化样品的光致发光谱进行研究,详细分析了各个光致发光峰的物理本质.     

高剂量Ge离子注入直接形成nc-Ge的研究

报道了分别采用剂量为1e1 6 ,1e1 7,5e 1 7和1e1 8cm- 2的高剂量Ge离子注入,不需退火即可在Si O2中直接形成Ge纳米晶的新现象.采用掠入射X射线衍射和激光喇曼谱等实验手段对样品进行了物相分析.结果表明,高剂量Ge离子注入可在SiO2 薄膜中直接形成Ge纳米晶(nc- Ge) ;非晶态Ge向晶态Ge发生相变的阈值剂量约为1e1 7cm- 2 ,离子注入直接形成的nc- Ge内部具有较大压应力,随着注入剂量的提高,nc- Ge的尺寸和含量均有提高.对纳米晶形成机理的研究认为,在Ge离子注入剂量达到阈值,此时膜中Ge非晶态团簇浓度达到饱和甚至过饱和,新入射的     

a-SiO_x∶H/a-SiO_y∶H多层薄膜微结构的退火行为

采用 PECVD技术在 P型硅衬底上制备了 a- Si Ox∶ H/a- Si Oy∶ H多层薄膜 ,利用 AES和 TEM技术研究了这种薄膜微结构的退火行为 .结果表明 :a- Si Ox∶ H/a- Si Oy∶ H多层薄膜经退火处理形成 nc- Si/Si O2 多层量子点复合膜 ,膜层具有清晰完整的结构界面 .纳米硅嵌埋颗粒呈多晶结构 ,颗粒大小随退火温度升高而增大 .在一定的实验条件下 ,样品在 650℃下退火可形成尺寸大小合适的纳米硅颗粒 .初步分析了这种多层复合膜形成的机理     

纳米硅薄膜的发光特性研究

研究了 nc- Si:H薄膜的光致发光 ( PL) ,分析了晶粒尺寸、温度对发光特性的影响。对发光样品 ,晶粒尺寸有一上限 ,其值在 4～ 5nm之间。在 10～ 77K,nc- Si:H薄膜的发光强度几乎没有变化 ;当温度高于 77K,发光强度指数式下降。随温度升高 ,发光峰位有少许红移。讨论了nc- Si:H光致发光机理 ,用量子限制 -发光中心模型对实验现象进行了解释。从载流子的激发、复合两方面讨论了发光过程 ,认为载流子在晶粒内部激发后 ,弛豫到晶粒界面的发光中心复合发光。     

SiO2膜的薄层化对自组织生长Si纳米量子点发光特性的影响

采用低压化学气相沉积方法,依靠纯SiH4气体的热分解反应,在SiO2表面上自组织生长了Si纳米量子点.实验研究了SiO2膜的薄层化对Si纳米量子点光致发光特性的影响.结果表明,当SiO2膜厚度减薄至6nm以下时,Si纳米量子点中的光生载流子会量子隧穿超薄SiO2层,并逃逸到单晶Si衬底中去,从而减少了光生载流子通过SiO2/Si纳米量子点界面区域内发光中心的辐射复合效率,致使光致发光强度明显减弱.测试温度的变化对Si纳米量子点光致发光特性的影响,则源自于光生载流子通过SiO2/Si纳米量子点界面区域附近非发光中心的非辐射复合所产生的贡献.     

SiO2膜的薄层化对自组织生长Si纳米量子点发光特性的影响

采用低压化学气相沉积方法,依靠纯SiH4气体的热分解反应,在SiO2表面上自组织生长了Si纳米量子点.实验研究了SiO2膜的薄层化对Si纳米量子点光致发光特性的影响.结果表明,当SiO2膜厚度减薄至6nm以下时,Si纳米量子点中的光生载流子会量子隧穿超薄SiO2层,并逃逸到单晶Si衬底中去,从而减少了光生载流子通过SiO2/Si纳米量子点界面区域内发光中心的辐射复合效率,致使光致发光强度明显减弱.测试温度的变化对Si纳米量子点光致发光特性的影响,则源自于光生载流子通过SiO2/Si纳米量子点界面区域附近非发光中心的非辐射复合所产生的贡献.     

Influence of Si nanocrystal distributed in the gate oxide on the MOS capacitance

In this paper, the authors have studied the influence of silicon nanocrystal (nc-Si) distributed in the gate oxide on the capacitance for the circumstances that the nc-Si does not form conductive percolation tunneling paths connecting the gate to the substrate. The nc-Si is synthesized by Si-ion implantation. The effective dielectric constant of the gate oxide in the nc-Si distributed region is calculated based on a sublayer model of the nc-Si distribution and the Maxwell-Garnett effective medium approximation. After the depth distribution of the effective dielectric constant is obtained, the MOS capacitance is determined. Two different nc-Si distributions, i.e., partial and full nc-Si distributions in the gate oxide, have been considered. The MOS capacitance obtained from the modeling has been compared to the capacitance measurement for a number of samples with various gate-oxide thicknesses, implantation energies and dosages, and an excellent agreement has been achieved for all the samples. A detailed picture of the influence of implantation energy and implantation dosage on the MOS capacitance has been obtained.     

1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O)composites prepared by RPECVD/oxidation process

Ultrathin nitride/oxide (~1.5/0.7 nm) dual layer gate dielectrics have been formed using remote plasma enhanced CVD of nitride onto plasma-grown oxide interface layers. High accumulation capacitance (1.72 μF/cm²) is measured and the equivalent oxide thickness is 1.6 nm after quantum effect corrections. Compared to 1.6 nm oxides, a tunneling current reduction of more than 100 fold is found for devices with 1.6 nm N/O dielectrics due to increased film thickness and interface nitridation. Hole channel mobility decreases by about 5%, yielding very good P-MOSFET current drive. Excellent dielectric reliability and interface robustness are also demonstrated for P-MOSFET's with N/O dielectrics     

对纳米硅薄膜高电导机制的探讨

使用超高真空PECVD薄膜沉积系统制备的纳米桂薄膜（nc－Si：H）具有高电导特性。为了探讨其导电机制，先使用K．Yoshida早期提出的两相无序结构有效电导模型分别对晶粒电导和界面电导进行了理论计算。指出，nc－Si：H股中高电导主要来自于细微晶粒的传导，界面可视之为非导体。另一方面，实验证实nc－Si：H股的电导率随平均品粒尺寸减少而增大，具有明显的小尺寸效应。文中首次提出，nc－Si：H膜的微晶粒具有异质结量子点（HQD）特性，并按此模型对nc－Si：H膜的电导率实验曲线进行了讨论。理论与实验结果符合得很好．又得出，硅薄膜结构在其晶态体积百分比Xc=0．30和0．70处呈现出两个明显的相变点。     

超薄氧化层中的中性陷阱对隧穿电流的影响和应变诱导漏电流

用数值分析的方法讨论了中性陷阱对超薄场效应晶体管(MOSFET )隧穿电流的影响.中性陷阱引起势垒的变化在二氧化硅的导带中形成一个方形的势阱.对于不同的势垒变化,计算了电子隧穿氧化层厚度为4nm的超薄金属氧化物半导体结构的电流.结果表明,中性陷阱对隧穿电流的影响不能被忽略,中性陷阱的存在使隧穿电流增加,并且通过这个简单的模型能够理解应变诱导漏电流的产生机制.     

Compact Modeling Methodology of Strained-Si Channel-on-Insulator (SSOI) MOSFETs

Compact physical models for SSOI MOSFETs are presented. The models consider specific features for strained-Si devices including SSOI such as mobility enhancement, band offsets, junction capacitance, and self-heating effects. All of the floating-body current components in conventional SOI structure, which are generation/recombination current, reverse-bias (band-to-band and trap-assisted) junction tunneling currents, gate-induced drain leakage current, gatebody oxide tunneling current, and impact ionization current are applied to the SSOI device, and their effects are discussed. The model validity is confirmed by fabricated 70?nm bulk-Si (control) and strained-Si devices.     

超薄氧化层中的中性陷阱对隧穿电流的影响和应变诱导漏电流

用数值分析的方法讨论了中性陷阱对超薄场效应晶体管(MOSFET )隧穿电流的影响.中性陷阱引起势垒的变化在二氧化硅的导带中形成一个方形的势阱.对于不同的势垒变化,计算了电子隧穿氧化层厚度为4nm的超薄金属氧化物半导体结构的电流.结果表明,中性陷阱对隧穿电流的影响不能被忽略,中性陷阱的存在使隧穿电流增加,并且通过这个简单的模型能够理解应变诱导漏电流的产生机制.     

PECVD淀积介质层对MOSFET性能的影响

通过对nMOS器件随天线比增加的阈值电压漂移、跨导变化，MOS电容在TDDB测试后的QBD退化分析来评估在RIE（Reactive Ion Etching）金属前PECVD-TEOS预淀积保护介质层的保护作用，实验结果表明此介质层没有起到足够的保护作用，反而会由于更长的等离子体工艺时间产生更严重的损伤问题。传统的电荷在硅片表面积累理论不足以解释此现象，本文从高能电子隧穿作用来分析此性能退化的原因。     

Low- and high-frequency capacitance of aluminum gallium nitride/gallium nitride heterostructures with interface traps

We have studied frequency dependence of capacitance properties of aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructures with interface traps at the AlGaN/GaN interface. We have shown that ability of charge in interface traps to respond to external measuring signal is responsible for the frequency dispersion of capacitance curves. The difference between capacitance curves measured at low and high frequencies in experimental structures is similar to the difference between simulated capacitances of the heterostructures with interface traps measured at low and high frequencies. At a high frequency when the charge in interface traps does not follow the measuring signal, the capacitance curves are only shifted in voltage compared to the curve of the structure without interface traps. But for low frequency a capacitance peak is observed. Interface traps hence contribute to experimentally observed capacitance dispersion.     

湿法腐蚀和干法刻蚀工艺对850 nmVCSEL高速调制性能的影响

垂直腔面发射激光器(VCSEL)以其低功耗、低阈值电流、高调制速率和易制作二维阵列器件等特点,广泛应用于短距离光互连领域.湿法腐蚀和干法刻蚀作为高速VCSEL台面结构制备的两种工艺,影响VCSEL氧化层的大小.文章研究了氧化层面积对寄生电容的影响,并计算得到7 μm氧化孔径下采用干法刻蚀工艺的垂直腔面发射激光器,相比较湿法腐蚀工艺,氧化层电容由902.23 fF减小至581.32 fF,谐振腔电容由320.72 fF减小至206.65 fF.通过对采用湿法腐蚀和干法刻蚀工艺制备的GaAs量子阱结构高速VCSEL进行小信号调制响应测试,结果表明,7μm氧化孔径下干法刻蚀VCSEL小信号调制带宽提高至16.1 GHz.     

The performance and reliability of PMOSFET's with ultrathin siliconnitride/oxide stacked gate dielectrics with nitrided Si-SiO2interfaces prepared by remote plasma enhanced CVD and post-depositionrapid thermal annealing

Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si₃N₄ onto oxides. Compared to PMOSFET's with heavily doped p⁺-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys