The performance and reliability of PMOSFET's with ultrathin siliconnitride/oxide stacked gate dielectrics with nitrided Si-SiO2interfaces prepared by remote plasma enhanced CVD and post-depositionrapid thermal annealing

Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si₃N₄ onto oxides. Compared to PMOSFET's with heavily doped p⁺-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys     

Electrical properties of high-quality ultrathin nitride/oxide stackdielectrics

The electrical properties of ultrathin nitride/oxide (N/O) stack dielectrics (2-4 nm), produced by in-situ jet vapor deposition (JVD), have been studied in some detail. Both theoretical calculation and experimental data show that the leakage current in the N/O stack is substantially lower than that in the single oxide layer of the same equivalent oxide thickness (EOT). When compared to the single nitride layer, the N/O stack yields a lower leakage current in the 3-nm thickness regime. In the 2-nm thickness regime, however, the leakage currents in the single nitride layer and the N/O stack are comparable. The tunneling current in the N/O stack depends not only on the thickness combination of the nitride and the oxide layers, but also on the injection polarity. Other important electrical properties of the N/O stack, including time-dependent-dielectric-breakdown (TDDB), stress-induced leakage current (SILC), carrier trapping, and interface characteristics are also reported. High quality field-effect transistors have been made of the N/O stack, and their properties will be reported     

High-quality ultrathin (1.6 nm) nitride/oxide stack gatedielectrics prepared by combining remote plasma nitridation and LPCVDtechnologies

Ultrathin nitride/oxide (N/O) gate dielectric stacks with equivalent oxide thickness of 1.6 nm have been fabricated by combining remote plasma nitridation (RPN) and low pressure chemical vapor deposition (LPCVD) technologies. NMOSFETs with these gate stacks exhibit good interface properties, improved subthreshold characteristics, low off-state currents, enhanced reliability, and about one order of magnitude reduction in gate leakage current to their oxide counterparts     

Ultrathin nitride/oxide (N/O) gate dielectrics forp+-polysilicon gated PMOSFETs prepared by a combined remoteplasma enhanced CVD/thermal oxidation process

Ultrathin nitride-oxide (N/O~1.5/2.6 nm) dual layer gate dielectrics have been incorporated into PMOSFETs with boron-implanted polysilicon gates. Boron penetration is effectively suppressed by the top plasma-deposited nitride layer leading to improved short channel performance as compared to PMOSFETs with oxide dielectrics. In addition, improved interface characteristics and hot carrier degradation immunity are also demonstrated for the devices with the N/O dual layer gate dielectrics     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²     

Hole tunneling current through oxynitride/oxide stack and the stackoptimization for p-MOSFETs

A systematic study on hole-tunneling current through both oxynitride and oxynitride/oxide (N/O) stack is for the first time presented based on a physical model. The calculations are in good agreement with the available experimental data. With a given equivalent oxide thickness (EOT), and under typical operating gate voltages (|Vg|<2 V), hole-tunneling current (essentially the gate current) is found to be lowest through the oxynitride or N/O stack with ~33% of nitrogen (N). An optimized N/O stack structure with 33% (atomic percentage) nitrogen and with a 3 Å oxide layer for keeping acceptable channel interface quality is proposed to project the N/O gate dielectrics scaling limit using in MOSFETs     

To optimize electrical properties of the ultrathin (1.6 nm)nitride/oxide gate stacks with bottom oxide materials andpost-deposition treatment

The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH₃/N₂O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O₂-grown bottom oxide. In post-deposition treatment, increasing NH₃ nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N₂O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH₃ nitridation step     

Tunneling leakage current in ultrathin (<4 nm) nitride/oxidestack dielectrics

The leakage current in high-quality ultrathin silicon nitride/oxide (N/O) stack dielectric is calculated based on a model of one-step electron tunneling through both the nitride and the oxide layers. The results show that the tunneling leakage current in the N/O stack is substantially lower than that in the oxide layer of the same equivalent oxide thickness (EOT). The theoretical leakage current in N/O stack has been found to be a strong function of the nitride/oxide EOT ratio: in the direct tunneling regime, the leakage current decreases monotonically as the M/O ratio increases, while in the Fowler-Nordheim regime the lowest leakage current is realized with a N/O EOT ratio of 1:1. Due to the asymmetry of the N/O barrier shape, the leakage current under substrate injection is higher than that under gate injection, although such a difference becomes smaller in the lower voltage regime. Experimental data obtained from high quality ultrathin N/O stack dielectrics agree well with calculated results     

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride（N/O）stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated，and ultra thin (＜2 nm＝ N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.     

超薄氮氧叠层栅介质的金属栅pMOS电容的电学特性

研究了高质量超薄氮化硅/氮氧化硅(N/O)叠层栅介质的金属栅pMOS电容的电学特性,制备了栅介质等效厚度小于2nm的N/O复合叠层栅介质,该栅介质具有很强的抗硼穿通能力和低的漏电流.实验表明这种N/O复合栅介质与优化溅射W/TiN金属栅相结合的技术具有良好的发展前景.     

Superthin O/N/O stacked dielectrics formed by oxidizing thinnitrides in low pressure oxygen for high-density memory devices

High-performance superthin oxide/nitride/oxide (O/N/O) stacked dielectrics have been successfully achieved by oxidizing thin nitride films in low-pressure dry-oxygen at 850°C for 30 min. Since the nitrides exhibit a better oxidation resistance to the low-pressure dry-oxygen than to the atmospheric-pressure dry-oxygen and wet-oxygen, the low pressure oxidation obtains a thinner oxidized nitride for the high-density dynamic-random-access-memories (DRAM's) and metal-oxide-nitride-oxide-semiconductor (MONO'S) memory devices. In addition, this dielectric possesses low leakage current and excellent time-dependent-dielectric-breakdown (TDDB) characteristics. Therefore, this novel recipe is promising for future ULSI technology     

Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing

A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectrics with equivalent oxide thickness (EOT) down to 14 /spl Aring/. Al/sub 2/O/sub 3/ was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650/spl deg/C in N/sub 2/ ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of k/spl sim/7.5 and leakage current of 2-3 orders of magnitude lower than SiO/sub 2/ are observed. The conduction mechanism in Al/sub 2/O/sub 3/ gate stack is shown to be Fowler-Nordheim (F-N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al/sub 2/O/sub 3/ gate stack/Si-substrate interfacial property. An optimal process control for preparing Al/sub 2/O/sub 3/ gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

恒压应力下超薄Si_3N_4/SiO_2叠层栅介质与SiO_2栅介质寿命比较

以等效氧化层厚度(EOT)同为2.1nm的纯SiO2栅介质和Si3N4/SiO2叠层栅介质为例,给出了恒定电压应力下超薄栅介质寿命预测的一般方法,并在此基础上比较了纯SiO2栅介质和Si3N4/SiO2叠层栅介质在恒压应力下的寿命.结果表明,Si3N4/SiO2叠层栅介质比同样EOT的纯SiO2栅介质有更长的寿命,这说明Si3N4/SiO2叠层栅介质有更高的可靠性.     

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

Effects of N distribution on charge trapping and TDDBcharacteristics of N2O annealed wet oxide

Wet pyrogenic oxide of different thicknesses was annealed in N₂O ambient and the N concentration in the films was studied by using SIMS (secondary ion mass spectroscopy). It was found that for a certain annealing time and temperature, the N concentration (at %) increases with decreasing wet oxide thickness and the location of the peak of N is observed near the interface of nitrided oxide and Si substrate. On the contrary, after nitridation the concentration of H is higher in the thicker wet oxide of thickness 100 Å and also does not change much from the surface to the interface. For the thinner wet oxide of thickness 40 Å, the concentration of H is less and decreases toward the interface. Gate dielectrics were characterized using high-frequency and quasi-static measurements. After a constant current stress, a large distortion was observed for the N₂O annealed wet oxide of 98 Å whereas for the N₂O annealed wet oxide of 51 Å the distortion was small. With increasing stressing time, hole trap is followed by electron trapping for the wet oxide of 98 Å whereas for the N₂O annealed wet oxide of 51 Å, hole trapping increases a little at the beginning and then saturates. From the TDDB characteristics, a longer t_BD was observed for N₂O annealed wet oxide of 51 Å compared to 98 Å. From the experimental results, it can be suggested that the improved reliability of thin gate oxide is due to the large amount of N concentration near the interface only. Hence for the device fabrication process, if the wet oxide is nitrided in N₂O ambient, the reliability of gate oxide will be improved in the ultrathin region     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

Two silicon nitride technologies for post-SiO2 MOSFETgate dielectric

P-MOSFETs with 14 Å equivalent oxide thickness (EOT) were fabricated using both JVD Si₃N₄ and RTCVD Si₃ N₄/SiO_xN_y gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO₂ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large     

Capacitance reconstruction from measured C-V in high leakage,nitride/oxide MOS

A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) curves in high leakage dielectric MOSFETs is presented. An RC network is used to accommodate the distributed nature of MOSFETs and an optimization technique is applied to extract the intrinsic gate capacitance. Applicability of the method is demonstrated for ultra-thin nitride/oxide (N/O ~1.4 nm/0.7 nm) composite dielectric MOSFETs     

Co-optimization of the metal gate/high-k stack to achieve high-field mobility >90% of SiO/sub 2/ universal mobility with an EOT=/spl sim/1 nm

HfO/sub 2/ and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO/sub 2/ universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-/spl kappa/ dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO/sub 2/ and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO/sub 2/ gate stack.