基于符号化矩的互连线统计时序建模

制造过程中的工艺偏差不能忽略,使得互连线延迟也成为具有一定概率分布的随机变量.为了快速准确地得到该概率分布,提出了一种新颖高效的符号化矩算法,并结合基于矩的延迟算法,得到了互连线延迟关于互连线物理参数偏差随机变量的闭合形式表达式,进而通过泰勒展开采用二阶非线性模型进行近似,最后运用特征函数和傅里叶变换直接计算得到互连线延迟的概率分布.该方法高效准确,避免了低效的蒙特卡罗模拟.实验表明,统计建模算法得到的延迟概率分布与蒙特卡罗结果相比有很好的精度,误差在0.000 093 656%以内.     

高速多芯片组件的互连延迟

高速、高性能MCM中，往往把电路设计在欠阻尼小振荡输出的工作状态，以保持信号在互连传输线中的快速和平稳传播。已有文献关于互连延迟的研究往往是针对过阻尼或欠阻尼大振荡工作状态，即对应于通常的IC和PCB互连。即使对高速VLSI互连延迟的研究，考虑到计算的复杂性和有效性，也往往只处理过阻尼和欠阻尼大振荡两种状态，因此给出的结果如果用于研究MCM互连延迟，误差相当大甚至无效，文中讨论了一种研究MCM互连延迟的方法，并给出了延迟在三种工作状态下与各物理参数之间的确定关系式。     

基于原点矩偏导的K分布杂波参数估计

K分布的参数估计研究对于雷达杂波特性预测和估计具有重要意义。基于矩估计的K分布参数估计方法通过联立不同阶原点矩进行参数求解,这些不同阶数下的联合,在数据长度受限情况下会产生误差。因此,通过计算原点矩偏导和原点矩之间的关系,推导出了一种新的K分布杂波参数估计方法。该方法在同阶原点矩的条件下进行参数估计,避免了不同阶原点矩之间的估计误差,具有更好的估计性能。通过仿真和实测杂波数据,分析比较了该方法与其他矩估计法的参数估计有效率和估计精度,该方法具有100%的估计有效率且估计精度更高。高阶矩对数据敏感,在矩估计法中应尽量选取低阶矩,通过合理选取阶数k可以得到较为理想的估计结果和精度。      

高速互连线CAD技术研究

采用边界积分方程结合矩量法计算高速互连线电磁参数,讨论了版图关键互连线提取技术和互连的ＳＰＩＣＥ模型建立技术,并用ＳＰＩＣＥ简要分析了互连线效应。     

一种稳定的RLC互连Π模型构建及其应用

基于RLC互连树节点导纳的低阶矩构建了一种稳定的互连π模型，并讨论了它在互连树延时和逻辑门延时估计中的应用．结果表明，该模型与已有方法相比精度有一定程度的提高．     

一种新的闭式空域格林函数及其在三维互连结构电容参数提取中的应用

该文提出了一种提取分层介质中三维静态闭式空域格林函数的通用算法,并成功地运用于三维多层多导体互连结构的电容参数提取。该算法在谱域等效传输线模型的基础上,应用Krylov子空间维数缩减技术求出谱域格林函数的有理逼近表达式,再由留数定理得到闭式空域格林函数。所得闭式空域格林函数结合矩量法可以方便地用于提取三维互连结构的电容参数。数值结果验证了方法的准确性和有效性。     

树状电路信号完整性符号化分析方法与应用

RLC树状电路的信号传输特性可以利用电路的高阶矩描述。电路的矩可以通过数值递归算法和符号化方法求得,其中基于矩决策图的符号化求解算法利用了决策图的共享特性,将大规模电路的矩进行符号化表示。通过引入树状电路之间的耦合电容和互感,利用电源分割理论,将树状电路矩的符号化算法进行推广,并构造一个耦合RLC树状电路的符号化仿真器,对耦舍互连线的信号完整性进行高效的分析和仿真。最终论证耦合RLC树状电路的串扰与电路参数之间的关系。     

一种提取多层介质多导体互连电磁参数的快速算法：有限差分－不变性测试方程法

本文首次利用ＭＥＩ方法计算了多层介质多导体互连的电容和电感矩阵．由于引入了测试环的概念，避免了多层结构的格林函数的推导和Ｓｏｍｍｅｒｆｅｌｄ积分的计算，同时也去掉了传统ＭＥＩ方法中ＭＥＩ系数与几何形状有关的假设．计算结果表明：本文提出的算法正确，与常见的算法如矩量法，边界元法和有限元法等方法相比，计算速度大大加快，并且对结构的适应性强，可以分析截面为任意形状且导体有耗的互连，因此该方法是一种提取电磁参数的快速算法．在计算得到的电容和电感矩阵的基础上，本文还利用双重波形收敛法计算了端接非线性负载的多导体互连各端口的瞬态响应．     

符号化矩敏感度方法在信号完整性优化中的应用

传统的线宽优化由于优化问题求解时运算复杂度的限制,在估计导线信号延迟和不同线网之间的串扰时都采用了非常简单的数学模型.利用符号化矩和矩敏感度运算可重复性强、运算效率高的特点,采用拉格朗日松弛法对更为精确的物理优化模型进行求解,该模型采用D2M作为节点延迟的估计,并且在估计串扰时考虑了干扰线网上信号跳跃对受干扰线网信号延迟影响的最坏情况.实验结果表明,该模型相对于传统的优化模型,有很高的精确度和可靠性.     

工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

AN IMPROVED MODEL OF THE INTERCONNECTION DELAY OF MULTICHIP MODULES

Moments of the system transfer function are closely related with the interconnection delays. Based on the first three moments, this paper presents an improved delay model for multichip module interconnection network. The model reveals an explicit causal relationship between delay of non-monotonic rising node voltage in tree-structure and design parameters. Obtained results not only provide a viable new method for computing interconnection delay, but also present a critical link between signal responses and design parameters. The derived formulas provide a tool to solve problems in the study of performance driven layout and routing algorithms.     

多芯片组件（MCM）的互连延时

高速、高性能MCM中，往往把电路设计在欠阻尼小振荡输出的工作状态，以保持信号在互连传输线中的快速和平稳传播。已有文献关于互连延时的研究往往是针对过阻尼或欠阻尼大振荡工作状态，即对应于通常的IC和PCB互连，即使对高速VLSI互连延时的研究，考虑到计算的复杂性和有效性，也往往只处理过阻尼和欠阻尼大振荡两种状态，因此若将给出的结果用于研究MCM互连延时，误差相当大甚至无效。本文提出了一种研究MCM互连延时的方法，并给出了延时在3种工作状态下与各物理参数之间的确定公式。     

A simplified synthesis of transmission lines with a tree structure

The limiting factor for high-performance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a generic distributedRLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform and delay in anRLC tree. The result on theRLC tree is then extended to the case of a tree consisting of transmission lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.     

Modeling and performance analysis of file transfer in a satellitewide area network

The authors consider the network modeling and performance analysis of multimedia file transfer between workstations connected to remotely located local area networks (LANs). The LANs are linked by a satellite wide-area network (SWAN) with a high bandwidth and high path delay. Four areas are addressed: (1) development of a fairly accurate interconnection network model using measured delay values for different network elements; (2) derivation of tight upper and lower bounds for the network throughput for both error-free and error-prone channels using mean value analysis; (3) validation of the model using computer simulation; and (4) analysis of the SWAN performance using numerical results for a wide range of parameters (file sizes, window size, link speed, number of workstations, etc.) for the case of a multimedia SWAN. Based on the analyses, performance bottlenecks for different operating conditions that could be used to evolve design criteria for better overall system performance are identified     

一种考虑自热效应的互连线缓冲器插入优化模型

Considering the self-heating effect,an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented.Based on the proposed resistance model and according to the trade-off theory,a novel optimization analytical model of delay,power dissipation and bandwidth is derived.The proposed optimal model is verified and compared based on 90 nm,65 nm and 40 nm CMOS technologies.It can be found that more optimum results can be easily obtained by the proposed model.This optimization model is more accurate and realistic than the conventional optimization models,and can be integrated into the global interconnection design of nano-scale integrated circuits.     

Mutual Synchronization Properties of a System of Two Oscillators with Sinusoidal Phase Detectors

Mutual synchronization between two geographically separated phase-locked oscillators is investigated for two different interconnection methods. This includes the so-called single-ended (uncompensated delay) and the double-ended (compensated delay) methods. Explicit formulas for determining the steady-state frequency and phase errors are developed for both methods. Necessary conditions for the existance of a synchronous state are derived in terms of basic system parameters. Finally, a comparison Of the methods of oscillator interconnection is made as a function of the uncompensated channel delays. Graphical results are presented which are useful in determining steadystate system performance.     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

基于SRAM的FPGA的互连时延模型

本文提出现场可编程门阵列FPGA中的互连资源MOS传输管时延模型.首先从阶跃信号推导出适合50%时延的等效电阻模型,然后在斜坡输入的时候,给出斜坡输入时的时延模型,并且给出等效电容的计算方法.结果表明,本文提出的时延模型快速并且足够精确.     

互连线网时延估算的一种有效算法

本文提出一种基于传递函数递推和系数匹配的互连线网时延估算法,该算法用二极点模型逼近互连线网的传递函数,仅通过计算某一频率点上的传递函数,就可利用导出的解析公式或拟合的经验公式进行快速时延估算,不必进行复杂的分量计算,算例表明,对于各个门限值,其计算结果均与ｓｐｉｃｅ计算的时延值发接近,计算量也比通常基于高阶分量计算的算法大为减少,在计算效率和模拟精度两方面得到较好折衷,对于互连线网时延估算具有实用