The effect of interconnection resistance on the performanceenhancement of liquid-nitrogen-cooled CMOS circuits

The interconnection is modeled as a distributed RLC line driven by an optimal configuration of cascaded inverters. The thin-film resistivity of pure aluminum has been measured to allow accurate prediction of the effect of interconnection resistance on performance. A critical interconnect length is defined as the point at which interconnect resistance begins to dominate propagation delay time. The critical interconnect length is computed at room temperature and liquid-nitrogen temperature for present-day and scaled CMOS technologies and compared to the maximum interconnect length expected in state-of-the-art VLSI circuits     

高速集成电路芯片内互连线的计算机辅助分析

分析了高速集成电路芯片内互连线的时域特性。首先运用全波方法提取互连线的频变等效电路参数。在此基础上运用数值反拉普拉斯变换 ( NILT)法分析互连电路的时域响应。在分析过程中 ,提出或运用了一些提高精度或效率的技术和方法。分析结果表明 ,该方法很适合高速集成电路芯片内互连线的计算机辅助分析。     

Overview of complementary GaAs technology for high-speed VLSIcircuits

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9 V have demonstrated power-delay products of 0.01 μW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor     

GMRES方法在3-D寄生电容计算中的应用

随着VLSI向深亚微米发展、集成电路密度不断提高,互连延迟成了加快器件速度的一个限制因素,由于互连延迟是由金属连线间的电阻及电容所产生的,因此萃取寄生参数的工作更显重要.文章使用GMRES方法求解了3-D寄生电容分析的复系数线性方程组,并将其与SOR迭代法相比较.这种方法可以降低方程的迭代次数约20%,并明显减少了方程的求解时间.     

MSI High-Speed Low-Power GaAs Integrated Circuits Using Schottky Diode FET Logic

A new planar high-density (10/sup -3/ mm/sup 2//gate) GaAs IC technology has been used for fabricating MSI digital circuits containing up to 75 gates/chip. These digital circuits have potential application for gigabit microwave data transmission and processor systems. The circuits consist of Schottky diode FET logic NOR gates, which have provided propagation delays in the 75-200-ps range with dynamic switching energies as low as 27 fJ/gate on ring oscillator structures. Power dissipation levels are compatible with future LSI/VLSI extensions. Operation of D flip-flops (DFF) as binary ripple dividers (/spl divide/2-/spl divide/8) was achieved at 1.9-GHz clock rates, and an 8:1 full-data multiplexer and 1:8 data demultiplexer were demonstrated at 1.1-GHz clock rates. This corresponds to equivalent propagation delays in the 100-175-ps range for these MSI circuits. Finally, a 3x3 parallel multiplier containing 75 gates functioned with a propagation delay of 172 ps/gate and with average gate power dissipations of as low as 0.42 mW/gate.     

Optical interconnections for VLSI systems

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The origins of the communication crisis are discussed. Those aspects of electrooptic technology that are applicable to the generation, routing, and detection of light at the level of chips and boards are reviewed. Algorithmic implications of interconnections are discussed, with emphasis on the definition of a hierarchy of interconnection problems from the signal-processing area having an increasing level of complexity. One potential application of optical interconnections is to the problem of clock distribution, for which a single signal must be routed to many parts of a chip or board. More complex is the problem of supplying data interconnections via optical technology. Areas in need of future research are identified.     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

Efficient calculation of interconnection delays on GaAs-based VHSIC

An efficient algorithm for the calculation of the propagation delays in the single-level high-density interconnections on GaAs-based VLSI is presented. The numerical technique can be applied to lossy as well as the lossless interconnection lines     

Delay time and signal propagation in large-scale integrated circuits

Delay time and signal propagation are considered for the logic circuits in future VLSI. When these are coupled to the necessity to dissipate power and to fundamental limits on the energy dissipation, a constraint which is almost geometry-independent is obtained. At one extreme, the fundamental limits suggest a minimum delay time of 0.01 ps. At the opposite extreme, values appropriate to conventional technology lead to a delay time per gate that is constrained to have a lower limit of about 0.2 ns in the wire-dominated chip.     

用修正特征法模型求解高速VLSI中有耗互连线的瞬态响应

本文提出了用于高速集成电路系统中有耗互连线瞬态响应求解的一个计算模型及其相应的算法。传统的特征法在用于求解无耗传输线或满足ＬＧ＝ＲＣ的有耗传输线时具有简单的递归形式和较高的计算效率,但不能用于一般的有耗传输线。本文在特征法的基础上,通过适当的参数修正,建立了一般有耗传输线瞬态响应的近似特征模型,导出了其对时间变量递归形式的计算公式。     

时延驱动的VLSI版图规划算法

本文提出了时延驱动布图规划的思想。在用改进的广义力矢量法优化功能单元间连线时延的同时，运算非线性规划的方法进一步优化关键路径上功能单元的时延及连线时延。结果表明，这是一种有效的优化版图时延的方法。     

Low-power CMOS/BiCMOS drivers and receivers for on-chipinterconnects

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed     

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization

Logic gates as repeaters (LGRs)-a methodology for delay optimization of CMOS logic circuits with resistance-capacitance (RC) interconnects is described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines, reducing the number of additional, logically useless inverters. Expressions for optimal segment lengths and gate scaling are derived. Considerations are presented for integrating LGR into a VLSI design flow in conjunction with related methods. Several logic circuits have been implemented, optimized and verified by LGR. Analytical and simulation results were obtained, showing significant improvement in performance in comparison with traditional repeater insertion, while maintaining low complexity and small area     

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the requirement of long interconnects in VLSI chips. Interconnects are known as the basic building block that can vary from size to size. They provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC models have already been defined to control these parameters but in this paper, authors have proposed a new improved Elmore delay estimation model (RC) to reduce delay and power consumption in interconnect circuits. An optimized Elmore delay calculation was performed for uniform and non-uniform wires to reduce the time constant of the interconnect circuits. Further, the proposed model is estimated and verified theoretically. A new improved RC model is compared to the designed π-model that shows remarkable results. We also observed the linear relationship of power consumption and delay for both the RC models and found that in π-model, upon decreasing the length of wire the power first increases then decreases but in the proposed model, the power first increases then remain constant and then further increases upon increasing the length of wire. Our proposed model shows the remarkable values as the average percentage improvement of power is 75.167% and delay as 74.714% is achieved using a uniform distribution.

     

互连线网时延估算的一种有效算法

本文提出一种基于传递函数递推和系数匹配的互连线网时延估算法,该算法用二极点模型逼近互连线网的传递函数,仅通过计算某一频率点上的传递函数,就可利用导出的解析公式或拟合的经验公式进行快速时延估算,不必进行复杂的分量计算,算例表明,对于各个门限值,其计算结果均与ｓｐｉｃｅ计算的时延值发接近,计算量也比通常基于高阶分量计算的算法大为减少,在计算效率和模拟精度两方面得到较好折衷,对于互连线网时延估算具有实用     

Pipelining communications in large VLSI/ULSI systems

A simple and very effective solution to the delay incurred while propagating data through long interconnection wires is presented. Such delays can be found in large VLSI/ULSI or wafer scale systems. The basic idea of the technique relies on the fragmentation of the wires and in reconnecting them with a special device called repeater in order to form a bidirectional pipeline. A method for determining the optimum configuration of the pipeline is presented. It is shown that, even in presence of an appreciable skew in synchronous systems, the technique improves the transmission speed by 150% for 32-byte messages, when a 10 cm 8-bit bus implemented in a 1.2 μm CMOS technology is used. The improvement increases for longer messages and for larger skews. It is also shown that the actual transmission time is close (to within a factor of 2) to the theoretical limit that could be achieved with a zero-length wire. A method based on repeaters operating at a multiple of the basic system clock frequency is also proposed. It is shown that this technique may speedup data transfer by an order of magnitude. The extension of the technique to asynchronous self-timed repeaters is also discussed. Finally, a VLSI implementation of the synchronous reconnection device is described     

Modeling of interconnect capacitance, delay, and crosstalk in VLSI

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations     

Current-mode signaling in deep submicrometer global interconnects

This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented.     

The effect of propagation delay uncertainty on the speed oftime-of-flight digital optoelectronic circuits

Time-of-flight synchronization is a new digital design methodology for optoelectronics that eliminates latches, allowing higher clock rates than alternative timing schemes. Synchronization is accomplished by precisely balancing connection delays. Circuits use pulse-mode signaling and clock gates to restore pulse timing. Many effective pipeline stages are created within combinational logic without extra hardware bounding the stages. Time-of-flight design principles are applicable to packet routing and sorting processors for optical interconnection networks. Circuits are unique because the clock rate is limited primarily by imprecision in propagation delay rather than absolute delay, as in circuits with latches. We develop a general model of delay uncertainty and focus on the effect that static and dynamic uncertainty accumulated over circuit paths has on the minimum feasible clock period. We present a method for traversing the circuit graph representation of a time-of-flight circuit to compute arrival time uncertainty at each pulse interaction point. Arrival time uncertainties give rise to pulse width and overlap constraints. From these constraints we formulate a constrained minimization to find the minimum clock period. We demonstrate our method on circuits implemented with 2×2 electro-optic switches and optical waveguides and find the electronic component of path uncertainty frequently limits speed     

An accurate analytical propagation delay model for high-speed CMLbipolar circuits

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison to SPICE circuit simulation results show excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determined the optimum current i₀ (or load resistor R_L) for a transistor of a certain emitter area when driven by a source of a voltage swing (ΔV) and slew time (t_r ). At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation delay time and improve the performance of high-speed CML circuits