Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

分析多芯片组件互连延时的一种新方法

随着多芯片组件工作频率的不断增加，信号延时受互连的影响越来越大，互连已成为决定系统性能的主要因素。延时与冲激响应有着密切的联系，本文采用系统冲激响应的低阶矩，基于双极点近似对互连的延时特性进行了研究。与已有的方法比较，本文的方法提高了极点选择的稳定性，适用于复杂的互连网络。举例证明了这种方法的有效性。     

Mesh routing topologies for multi-FPGA systems

There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper, we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce interchip delays by more than 60% over the basic four-way Mesh     

A Note on the Statistical Dynamics of Two Mutually Phase-Locked Oscillators

This note demonstrates that the behavior of two mutually synchronized phase-locked oscillators using delay compensation is equivalent to that of a first-order loop with the loop parameters degraded by the residual uncompensated delays of the system. In particular, the probability density of phase differences between the two oscillators is derived and the numerical results are also presented. The cycle slipping rate is easily obtained from this density.     

高速多芯片组件的互连延迟

高速、高性能MCM中，往往把电路设计在欠阻尼小振荡输出的工作状态，以保持信号在互连传输线中的快速和平稳传播。已有文献关于互连延迟的研究往往是针对过阻尼或欠阻尼大振荡工作状态，即对应于通常的IC和PCB互连。即使对高速VLSI互连延迟的研究，考虑到计算的复杂性和有效性，也往往只处理过阻尼和欠阻尼大振荡两种状态，因此给出的结果如果用于研究MCM互连延迟，误差相当大甚至无效，文中讨论了一种研究MCM互连延迟的方法，并给出了延迟在三种工作状态下与各物理参数之间的确定关系式。     

AN IMPROVED MODEL OF THE INTERCONNECTION DELAY OF MULTICHIP MODULES

Moments of the system transfer function are closely related with the interconnection delays. Based on the first three moments, this paper presents an improved delay model for multichip module interconnection network. The model reveals an explicit causal relationship between delay of non-monotonic rising node voltage in tree-structure and design parameters. Obtained results not only provide a viable new method for computing interconnection delay, but also present a critical link between signal responses and design parameters. The derived formulas provide a tool to solve problems in the study of performance driven layout and routing algorithms.     

GMRES方法在3-D寄生电容计算中的应用

随着VLSI向深亚微米发展、集成电路密度不断提高,互连延迟成了加快器件速度的一个限制因素,由于互连延迟是由金属连线间的电阻及电容所产生的,因此萃取寄生参数的工作更显重要.文章使用GMRES方法求解了3-D寄生电容分析的复系数线性方程组,并将其与SOR迭代法相比较.这种方法可以降低方程的迭代次数约20%,并明显减少了方程的求解时间.     

多芯片组件（MCM）的互连延时

高速、高性能MCM中，往往把电路设计在欠阻尼小振荡输出的工作状态，以保持信号在互连传输线中的快速和平稳传播。已有文献关于互连延时的研究往往是针对过阻尼或欠阻尼大振荡工作状态，即对应于通常的IC和PCB互连，即使对高速VLSI互连延时的研究，考虑到计算的复杂性和有效性，也往往只处理过阻尼和欠阻尼大振荡两种状态，因此若将给出的结果用于研究MCM互连延时，误差相当大甚至无效。本文提出了一种研究MCM互连延时的方法，并给出了延时在3种工作状态下与各物理参数之间的确定公式。     

Two effective methods to mitigate soft error effects in SRAM-based FPGAs

This paper proposes an effective architecture that can mitigate Single Event Upset (SEU) effects in SRAM-based FPGAs. The architecture employs two different methods in both logic and interconnection resources. The logic resources utilize a new function generator that can tolerate 100% of single faults in its configuration memory while it can generate all the k-input Boolean functions. In the interconnection resources, a kind of formation redundancy that can detect 94% of single faults in its configuration memory is applied. Both methods are based on an interesting relation in Boolean functions, identified as mapping. By this concept, a Boolean function is generated by modifying the inputs of other Boolean functions. The effectiveness of the proposed architecture is procured by a standard fault injection tool; moreover, different parameters such as required area, power, and delay are achieved by using synopsis® synthesis tool. The results show that the area, power, and delay overheads are respectively 179%, 94%, and 60% in comparison with the simple architecture.     

研究多芯片组件互连延迟的一种新方法

延迟与冲激响应的矩有密切的关系,文中给出了建立在前三个矩基础上的多芯片组件互连延迟模型。该模型揭示了非单调输出树状结构ＭＣＭ互连网络的延迟与各设计参数之间的明确关系,因此它可以作为一种计算延迟的有效方法。进一步的研究结果还给出了输出响应与各设计参数之间的关系式,因此该模型又为研究面向性能的布局、布线算法中的有关问题提供了一种解决的途径。     

用修正特征法模型求解高速VLSI中有耗互连线的瞬态响应

本文提出了用于高速集成电路系统中有耗互连线瞬态响应求解的一个计算模型及其相应的算法。传统的特征法在用于求解无耗传输线或满足ＬＧ＝ＲＣ的有耗传输线时具有简单的递归形式和较高的计算效率,但不能用于一般的有耗传输线。本文在特征法的基础上,通过适当的参数修正,建立了一般有耗传输线瞬态响应的近似特征模型,导出了其对时间变量递归形式的计算公式。     

互连线网时延估算的一种有效算法

本文提出一种基于传递函数递推和系数匹配的互连线网时延估算法,该算法用二极点模型逼近互连线网的传递函数,仅通过计算某一频率点上的传递函数,就可利用导出的解析公式或拟合的经验公式进行快速时延估算,不必进行复杂的分量计算,算例表明,对于各个门限值,其计算结果均与ｓｐｉｃｅ计算的时延值发接近,计算量也比通常基于高阶分量计算的算法大为减少,在计算效率和模拟精度两方面得到较好折衷,对于互连线网时延估算具有实用     

A comparative study of single-section polarization-mode dispersion compensators

This paper shows how to use multiple importance sampling to study the performance of polarization-mode dispersion (PMD) compensators with a single differential group delay (DGD) element. We compute the eye opening penalty margin for compensated and uncompensated systems with outage probabilities of 10/sup -5/ or less with a fraction of the computational cost required by standard Monte Carlo methods. This paper shows that the performance of an optimized compensator with a fixed DGD element is comparable to that of a compensator with a variable DGD element. It also shows that the optimal value of the DGD compensator is two to three times larger than the mean DGD of the transmission line averaged over fiber realizations. This technique can be applied to the optimization of any PMD compensator whose dominant sources of residual penalty are both the DGD and the length of the frequency derivative of the polarization-dispersion vector.     

异地综合试验互联网络技术研究

文中以民用飞机电子系统的试验互联体系为例，介绍了一种试验互联网络设计技术。针对在大型复杂电子系统研发过程中，分布式试验设施之间测试信号传输需满足传输时延和品质保真的要求，采用基于光纤互联网络的多电信号适配技术，通过核心部件光纤交换机和信号中继转换装置构建了可级联扩展的试验互联网络体系。根据对原型系统的测试分析表明，在确保信号传输品质的情况下，在500 m传输范围内试验互联网络对典型信号的延时一般不超过60 μs     

可重构硬件芯片级故障定位与自主修复方法

 外部集中控制的可重构硬件容错系统,其重构控制算法复杂、重构时间开销大,且存在单点失效问题.本文研究芯片级分布式在线自主容错技术,提出了能够实现芯片级自修复的新型可重构硬件细胞阵列结构,阐述了互连资源的在线故障定位和自主修复方法.设计了功能细胞电路和容错开关块电路,采用分段定位法检测互连资源中多路器故障和连线开路故障,通过重配置布线和线移位操作分别实现多路器与连线故障自修复.以4位串并乘法器电路为例进行实验验证,分析了容错设计的硬件开销与时间开销,实验结果表明新方案的容错时间短、资源利用率高.     

High-Speed Packet Switching Systems for Multimedia Communications

High-speed packet switching (HPS) systems can Provide flexible, economical, high-quaiity services for integrated voice, video, and data communications. To realize such HPS systems, methods have been developed to bring about high-speed protocol processing as well as a system architecture for facilitating high-throughput switching. Adopting the parallel processing algorithm into protocol processing allows us to achieve high-speed packet protocol processing of about 100 times faster than conventional processing. Furthermore, a fully distributed system architecture in addition to hierarchical interconnection networks can achieve high-capacity packet switching systems. The proposed HPS system is thus capable of accommodating lines of up to 10-50 Mbits/s, of providing high-throughput switching capability of 1 000 000 packets/s, and of having an average delay of less than 2 ms. Furthermore, an evaluation of network delay performances of video conferencing and voice communications indicate that HPS systems are quite suitable for handling such multimedia communications.     

ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture

Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%–88.6% while the critical path delay is reduced to 66.1%–90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.     

可重构阵列处理器光电混合互连原型系统实现

高效视频编码(HEVC)标准在提升编码性能的同时,对系统带宽提出了更高的要求。传统电互连方式存在带宽小和时延大的问题,而光互连的高带宽和低功耗为片上资源数据通信提出了新的解决方案。然而由于工艺水平的限制,集成光器件无法在现场可编程门阵列(FPGA)芯片内部实现。采用片外光器件模拟片上光互连系统可以达到原型验证的目的。文章基于BEE4开发平台在单片上采用电互连方式进行数据通信,在Xilinx V6系列芯片间通过接入4通道小型可插拔+(QSFP+)光模块搭建光通信链路,构建光通信网络,实现了光电混合互连网络原型系统。以分辨率176×144的标准测试序列akiyoqcif176×144.yuv为例进行测试,实验结果表明,以光链路替代片间电通信能够正确实现,且板间传输时间仅为电互连的一半,综合频率为51.327 MHz。     

Exact analytical evaluation of second-order PMD impact on the outage probability for a compensated system

An exact analytical method for evaluating the outage probability due to second-order polarization mode dispersion in a system with first-order compensation is presented. In an uncompensated system the outage is mainly due to the mean differential group delay, whereas higher order effects have low impact. It is shown that in a compensated system all orders contribute to the outage probability, whereas accounting for exact second-order only gives a slight overestimate. Approximate second-order models leaving residual higher order effects may lead to very different outage probabilities.     

Determination of mechanical and electronic shifts for pinhole SPECT using a single point source

The effects of uncompensated electronic and mechanical shifts may compromise the resolution of pinhole single photon emission computed tomography. The resolution degradation due to uncompensated shifts is estimated through simulated data. A method for determining the transverse mechanical and axial electronic shifts is described and evaluated. This method assumes that the tilt of the detector and the radius of rotation (ROR) are previously determined using another method. When this assumption is made, it is possible to determine the rest of the calibration parameters using a single point source. A method that determines the electronic and mechanical shifts as well as the tilt has been previously described; this method requires three point sources. It may be reasonable in most circumstances to calibrate tilt much less frequently than the mechanical shifts since the tilt is a property of the scanner whereas the mechanical shift may change every time the collimator is replaced. An alternative method for determining the ROR may also be used. Lastly, we take the view that the transverse electronic shift and the focal length change slowly and find these parameters independently.