| AN IMPROVED MODEL OF THE INTERCONNECTION DELAY OF MULTICHIP MODULES |
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| 作者姓名： | Lai Jinmei Li Ke Lin Zhenghui Huang Peizhong |
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| 作者单位： | Lai Jinmei Li Ke Lin Zhenghui Huang Peizhong(information and Electronic Engineering Dept.，Zhejiang University，Hangzhou 310027)(Electronic Information School，Shanghai Jiaotong University，Shanghai 200030) |
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| 摘 要： | Moments of the system transfer function are closely related with the interconnection delays. Based on the first three moments, this paper presents an improved delay model for multichip module interconnection network. The model reveals an explicit causal relationship between delay of non-monotonic rising node voltage in tree-structure and design parameters. Obtained results not only provide a viable new method for computing interconnection delay, but also present a critical link between signal responses and design parameters. The derived formulas provide a tool to solve problems in the study of performance driven layout and routing algorithms.
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An improved model of the interconnection delay of multichip modules |
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| Lai Jinmei Li Ke Lin Zhenghui Huang Peizhong.AN IMPROVED MODEL OF THE INTERCONNECTION DELAY OF MULTICHIP MODULES[J].Journal of Electronics,1999,16(3):284-288. |
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| Authors: | Jinmei Lai Ke Li Zhenghui Lin Peizhong Huang |
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| Affiliation: | (1) Information and Electronic Engineering Dept., Zhejiang University, 310027 Hangzhou;(2) Electronic Information School, Shanghai Jiaotong University, 200030 Shanghai |
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| Abstract: | Moments of the system transfer function are closely related with the interconnection delays. Based on the first three moments, this paper presents an improved delay model for multichip module interconnection network. The model reveals an explicit causal relationship between delay of non-monotonic rising node voltage in tree-structure and design parameters. Obtained results not only provide a viable new method for computing interconnection delay, but also present a critical link between signal responses and design parameters. The derived formulas provide a tool to solve problems in the study of performance driven layout and routing algorithms. |
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| Keywords: | Multichip module Interconnection delay Interconnect transmission lines Moment generation Moment matching |
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