ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture

Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%–88.6% while the critical path delay is reduced to 66.1%–90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.     

基于IEEE 802.16-2004标准的Mesh机制

MESH网络架构引入多跳的方式完成长距离通信，取得了覆盖范围和吞吐量的性能优化。本文介绍了基于IEEE 802．16-2004标准的Mesh机制，基于对协议的理解，对Mesh网络中新节点接入过程和协议中对调度的规定进行了详细阐述。     

Crossbar光交换网络

Crossbar网络是实现高速并行光学处理的一种最重要而有效的光交换网络结构。作为一种无阻塞网络,Crossbar网络具有简单性,易于实现控制,适合于构成光开关矩阵。总结和分析了近20多年来发展的Crossbar光交换网络,介绍了不同Crossbar光交换网络的原理、结构和性能,分析了Crossbar光交换网络的关键技术。目前光学互连网络的发展方向是实现集成大规模光互连。可以预见光学互连网络会朝着更加实用化的方向发展,并在其应用领域发挥越来越重要的作用。     

Accurate Interconnection Length and Routing Channel Width Estimates for FPGAs

提出了一种新的FPGA互连预测算法,包括互连长度估计算法和通道宽度估计算法.实验结果表明,与现有算法相比,该估计算法能获得更准确的估计结果.     

准确的FPGA互连长度和通道宽度估计

提出了一种新的FPGA互连预测算法,包括互连长度估计算法和通道宽度估计算法.实验结果表明,与现有算法相比,该估计算法能获得更准确的估计结果.     

高性能可编程互连资源设计研究

传统的可编程互联结构在短距离互连上往往采用单管、中距离上有双向线,这使得在CLB中查找表(LUT)数目变大后,互连上的延迟会随线长增加而呈指数增长.本文提出了一种改进的高性能互连结构,改进了短、中和长距离互连,使得其在CLB中LUT数目增加的情况下让芯片拥有更好的互连延迟特性,通过对这种互连结构和传统的互连结构进行建模...     

Wave-pipelined intra-chip signaling for on-FPGA communications

On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by proposing a novel wave-pipelined signaling scheme to achieve substantial throughput improvement in FPGAs. A new analytical model capturing the electrical characteristics in FPGA interconnects is presented. Based on the model, throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous links. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that the wave-pipelined approach can achieve up to 5.7 times improvement in throughput and 13% improvement in power consumption versus conventional delay-based on-chip communication schemes. Also, trade-offs between power, throughput and area consumption between the proposed and conventional designs are studied. The wave-pipelining approach provides a new alternative for on-FPGA communications and can potentially become a promising solution to mitigate the future interconnect scaling challenge.     

An efficient logic emulation system

The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGAs for logic. Several designs, including a 32-b CPU datapath, have been automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development, and special-purpose execution     

Fine-grained and coarse-grained behavioral partitioning witheffective utilization of memory and design space exploration formulti-FPGA architectures

Reconfigurable computers (RCs) host multiple field programmable gate arrays (FPGAs) and one or more physical memories that communicate through an interconnection fabric. State-of-the-art RCs provide abundant hardware and storage resources, but have tight constraints on FPGA pin-out and inter-FPGA interconnection resources. These stringent constraints are the primary impediment for multi-FPGA partitioning tools to generate high-quality designs, in this paper, we present two integrated partitioning and synthesis approaches for RCs. The first approach involves fine-grained partitioning of a scheduled data-flow graph (DFG, or an operation graph), and the second involves a coarse-grained partitioning of an unscheduled control data flow graph (CDFG, or a block graph). A hardware design space exploration engine is integrated with the block graph partitioner that dynamically contemplates multiple schedules during partitioning. The novel feature in the partitioning approaches is that the physical memory in the RC is effectively used to alleviate the FPGA pin-out and inter-FPGA interconnection bottle-neck. Several experiments have been conducted, targeting commercial multi-FPGA boards, to compare the two partitioning approaches, and detailed summaries are presented     

Using the multistage cube network topology in parallelsupercomputers

A critical component of any large-scale parallel processing system is the interconnection network that provides a means for communication along the system's processors and memories. Attributes of the multistage cube topology that have made it an effective basis for interconnection networks and the subject of much ongoing research are reviewed. These attributes include O(N log₂N) cost for an N-input/output network, decentralized control, a variety of implementation options, good data-permuting capability to support single-instruction-stream/multiple-data-stream (SIMD) parallelism, good throughput to support multiple-instruction-stream/multiple-data-stream (MIMD) parallelism, and ability to be partitioned into independent subnetworks to support reconfigurable systems. Examples of existing systems that use multistage cube networks are considered. The multistage cube topology can be converted into a single-stage network by associating with each switch in the network a processor (and a memory). Properties of systems that use the multistage cube network in this way are examined     

三级Clos网络中分布式调度算法研究

调度算法用于解决交换网络输出端口竞争问题.鉴于现有三级Clos网络调度算法存在实现复杂、性能无法保证的缺点,本文提出了一种利于分布式调度的三级Clos网络结构和相应的负载均衡调度思想,并给出了一种简单负载均衡调度算法.采用这种新结构和相应的调度思想不仅可以简化三级Clos网络的调度,而且可以充分利用现有单Crossbar网络调度的研究成果,保证算法性能.文中通过理论和仿真分析证明基于这种思想的调度算法比现有算法具有很大的优越性.     

A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs

SRAM-based Field Programmable Gate Arrays (SRAM-FPGA) are more and more employed in today’s applications. In space and avionic applications their operations might be harmed by occurrence of radiation-induced upsets, or Single Event Upsets (SEU), which require the adoption of mitigation techniques. In these devices the majority of the configuration memory rules the interconnection setting. In devices employing “switch matrix” routing, the density of interconnections in switch arrays seems to be a critical point. The higher the interconnection density (i.e., the higher the number of interconnection segments activated by the same switch matrix), the higher the probability of an upset due to a configuration bit controlling the switch matrix. This paper presents an approach to estimate the SEU sensitivity of programmable interconnections of SRAM-based FPGAs as a function of the density of programmable interconnection points inside device configurable logic blocks. A probabilistic model of the SEU effects in programmable interconnection points of Xilinx SRAM-FPGAs is described. The application of the proposed approach to a set of sample designs is illustrated.     

无线光互连技术发展综述

人们对无线宽带通信技术的需求在近些年稳步增长.无线电波频谱的带宽限制和频带拥堵,通过微波无线网络的发展已经有了明显的改善.然而,无线光互连技术才能使得数据传输带宽达到理想的要求.作为许多无线通讯系统的最终方案,无线光互连也被选择为长期的解决策略.并且,无线光互连的大量优势还没有得到完全的发掘,许多基础性和应用性的研究还需要在实验层面和商业应用层面加以深入.国外,Gb/s的无线光传输已经在实验室中得到了验证,然而,可用的室内无线光互连系统也仅仅达到了155Mb/s的速度.下面将着重从收发系统、性能及安全性方面对无线光互连技术作一概况阐述.     

一种组播路由算法

随着组播业务的急剧增多,组播技术(Multicast)日益重要.在组播技术中组播路由算法是一项关键技术.主要介绍了两种组播路由算法,一种是适用于任意网络拓扑的启发式路由算法(RST),另一种是基于Mesh网络拓扑的启发式路由算法.     

An all-optical implementation of a 3-D crossover switching network

One of the more promising interconnection schemes proposed for use in photonic switching networks is the crossover interconnection network; however, reported implementations of the crossover have been limited in size and complexity. A large-scale cascadable implementation of the optical crossover network that capitalizes on planar symmetric self electrooptic effect device (S-SEED) arrays is discussed. A fully functional experimental prototype with 32 inputs and 32 outputs that was operated at a maximum rate of 55.7 kb/s is also discussed. It is also shown that S-SEED arrays can be operated as simple two-input two-output nodes (called 2-modules) within a controllable network     

LOOKNoC: a low-loss,non-blocking,scalable passive optical interconnect network-on-chip architecture

Low-loss, non-blocking, scalable passive optical interconnect network on-lhip ( LOOKNoC) structure was proposed based on 2 *2 optical exchange switches, using wavelength division multiplexing (WDM) technology to expand to 8 *8, 16 *16, 32 *32, 64 *64 passive optical interconnection networks, which can achieve non-blocking communication. The experimental results show that based on the 16 *16 optical interconnection network structure, the number of microring resonators (MRs) in LOOKNoC was reduced by 90.9%, 90.9%, 20.0% and 75.0% compared with the generic wavelength-routed optical router (GWOR), λ-router topology and CrossBar structure. By testing the performance parameters based on the structure of 16 *16 by the OMNET + + platform, as the result shows, the average insertion loss of LOOKNoC is 3.0%, 11.6%, 4.8% and 16.7% less than that of     

无线网状网与协作中继技术

无线网状网已经成为无线宽带通信领域的研究热点,但是基于交换技术的无线网状网因为其将整个网络看作是一个IP子网而无法适用于大范围的覆盖。在无线链路中采用协作中继,可以提高无线链路的传输速率及传输可靠性。同时采用基于网络层路由技术的无线网状网技术,可以实现整个无线网状网的频谱效率提升和厂域覆盖。不过,由于标准化、关键技术研究以及产业化推进方面还存在许多问题,使得协作中继技术在无线网状网中的应用面临着巨大挑战。     

Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs

Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.     

一种基于标准CMOS工艺的单片光互连

探索了采用标准CMOS工艺实现单片光互连的可行性。采用特许(Chartered)半导体公司3.3V、0.35μm标准模拟CMOS工艺设计并制造了一种单片光互连系统,并用两种结构研究了衬底噪声耦合对互连性能的影响。测试结果表明:该光互连系统可工作于几×103Hz,验证了基于标准CMOS工艺的单片光互连系统是可行的。     

Reconfigurable SIMD massively parallel computers

This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved, and to remove faulty processors from the network so that the system operation can be kept uninterrupted while maintaining the same or slightly degraded efficiency. Several existing reconfigurable single instruction multiple data (SIMD) parallel architectures and their reconfiguration mechanism are described, the effectiveness of algorithm mapping, through reconfiguration, is demonstrated, and fault-tolerant schemes via reconfiguration are discussed