共查询到20条相似文献,搜索用时 109 毫秒
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研究了在不同恒定温度应力条件下某型号驱动器的模拟集成电路的加速退化试验.首先,确定了该型驱动器的敏感参数,并建立了敏感参数的退化模型;然后,计算得到了器件在加速应力下的伪寿命;最后,利用阿伦尼斯模型对伪寿命数据进行分析,外推得到了器件的激活能及其在正常工作应力条件下的寿命信息. 相似文献
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在综述大功率AlGaN/GaN HFET性能退化实验结果的基础上,研究了器件退化与电流崩塌间的关联。分析了现有各类器件失效模型的优点和不足之处。通过沟道中强电场和热电子分布的研究,完善了热电子触发产生缺陷陷阱的器件退化模型。使用这一模型解释了实验中观察到的各类性能退化现象,指出优化设计异质结构可以有效减弱GaN HFET的性能退化。最后提出减弱器件性能退化的方法和途径。 相似文献
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A new integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. This reliability simulation tool incorporates: (1) an accurate 1-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors; and (2) physical models for both fundamental device-degradation mechanisms (charge trapping and interface trap generation). Hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. A repetitive simulation scheme ensures accurate prediction of the circuit-level degradation process under dynamic operating conditions. The evolution of hot-carrier related damage in each device is automatically simulated at predetermined time intervals, instead of extrapolating the long-term degradation using only the initial simulation results. Thus, the gradual variation of dynamic stress conditions is accounted for during the long-term damage estimates 相似文献
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施主型界面态引起深亚微米槽栅PMOS特性的退化 总被引:1,自引:1,他引:0
基于流体动力学能量输运模型 ,对沟道杂质浓度不同的槽栅和平面 PMOSFET中施主型界面态引起的器件特性的退化进行了研究 ,并与受主型界面态的影响进行了对比 .研究结果表明同样浓度的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件 ,且 N型施主界面态密度对器件特性的影响远大于 P型界面态 ,N型施主界面态引起器件特性的退化趋势与 P型受主界面态相似 ,而 P型施主界面态则与 N型受主界面态相似 .沟道杂质浓度不同 ,界面态引起的器件特性的退化则不同 相似文献
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基于流体动力学能量输运模型 ,对沟道杂质浓度不同的深亚微米槽栅和平面 PMOSFET中施主型界面态引起的器件特性的退化进行了研究 .研究结果表明同样浓度的界面态密度在槽栅器件中引起的器件特性的漂移远大于平面器件 ,且电子施主界面态密度对器件特性的影响远大于空穴界面态 .特别是沟道杂质浓度不同 ,界面态引起的器件特性的退化不同 .沟道掺杂浓度提高 ,同样的界面态密度造成的漏极特性漂移增大 . 相似文献
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The physical models and an integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model includes both fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions 相似文献
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界面态引起的器件特性的退化是深亚微米微米器件失效的一个重要因素,本文基于流体动力学能量输运模型,对沟道杂质浓度不同的槽机和平面PMOSFET中受主型界面态引起的器件特性的退化进行了分析,研究结果表明同样浓度的界面态浓度在槽栅器件中引起的器件特性的漂移远大于平面器件,且P型受主型界面态度对器件特性的影响也远大于N型界面态,沟道杂质浓度不同,界面态引起的器件特性的退化不同。 相似文献
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Meng Zhang 《Microelectronics Reliability》2010,50(5):713-716
Degradation of n-type low temperature polycrystalline silicon thin film transistors under drain pulse stress is first investigated. Stress parameters are pulse amplitude, frequency and transition time. Device degradation is found to be dominated by a dynamic hot carrier effect, which is independent of pulse falling time but depends on pulse rising time. Shorter rising time brings larger device degradation. Based on experimental results and device simulation, a PN junction degradation model taking trap related carrier emission and trapping into account is proposed. 相似文献
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Pouydebasque A. Charbuillet C. Gwoziecki R. Skotnicki T. 《Electron Devices, IEEE Transactions on》2007,54(10):2723-2729
We present here a simple analytical model of the subthreshold slope of CMOS devices that successfully describes the long-channel plateau, the initial improvement for medium gate lengths, and the final degradation for short gate lengths. The model is based on the voltage-doping transformation (VDT) that leads to a new term in the subthreshold slope expression, explaining the degradation of the slope at very short channels. The potential minimum at the virtual cathode was expressed using a semiempirical expression that allows our model to fit to data that were extracted from simulation in a wide range of device parameters. Finally, the new slope model successfully reproduced experimental data that were measured on devices based on 90- and 65-nm technologies, demonstrating the validity of our model for advanced bulk CMOS technologies. 相似文献