不同HALO掺杂剂量的超薄栅pMOSFET的退化

研究了热载流子应力下栅厚为2 .1nm ,栅长为0 .135μm的p MOSFET中HAL O掺杂剂量与器件的退化机制和参数退化的关系.实验发现,器件的退化机制对HAL O掺杂剂量的改变不敏感,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随着HAL O掺杂剂量的增加而增加.实验同时发现,器件参数的退化不仅与载流子迁移率的退化、漏串联电阻增大有关,而且与阈值电压的退化和应力前阈值电压有关.     

氧等离子气氛中NMOS器件的性能退化

文章描述了氧等离子干法剥离光刻胶中MOS器件的性能退化问题,并且制备了不同天线比AR(Antenna Ratio),相同器件结构的NMOS器件来检测器件的退化.实验结果发现栅漏电流密度Jg和阈值电压Vt漂移会随着Al的天线面积的增加而非线性地增加,尤其表现在阈值电压漂移上.运用增加电流应力时间的测试来模拟器件在等离子反应腔中所受的实际应力,发现了与天线比增加时阈值电压变化趋势相同,表明在氧等离子气氛中器件受到了负电应力的影响.最后,基于此次实验的结果,在器件的设计,工艺参数的制定方面提出了一些减小干法剥离光刻胶工艺带来器件性能退化的建议.     

一种非对称双栅应变硅HALO掺杂沟道MOSFET阈值电压解析模型

提出了一种非对称双栅应变硅HALO掺杂沟道金属氧化物半导体场效应管结构.该器件前栅和背栅由两种不同功函数的金属构成,沟道为应变硅HALO掺杂沟道,靠近源区为低掺杂区域,靠近漏区为高掺杂区域.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,分别求解了前背栅表面势、前背栅表面电场及前背栅阈值电压,建立了双栅器件的表面势、表面电场和阈值电压解析模型.详细讨论了物理参数对解析模型的影响.研究结果表明,该器件能够很好的抑制短沟道效应、热载流子效应和漏致势垒降低效应.模型解析结果与DESSIS仿真结果吻合较好,证明了该模型的正确性.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

空间辐射环境下SiC功率MOSFET栅氧长期可靠性研究

利用等效1 MeV中子和γ射线对1200 V SiC功率MOSFET进行辐射,研究了电离损伤和位移损伤对器件的影响,并分析了辐射后器件栅氧长期可靠性。结果表明：中子辐射后器件导通电阻发生明显退化,与辐射引入近界面缺陷降低载流子寿命和载流子迁移率有关。时间依赖的介质击穿(TDDB)结果表明,栅泄漏电流呈现先增加后降低趋势,与空穴捕获和电子捕获效应有关。中子辐射后栅漏电演化形式未改变,但氧化层击穿时间增加,这是中子辐射缺陷增加了Fowler-Nordheim(FN)隧穿势垒的缘故。总剂量辐射在器件氧化层内引入陷阱电荷,使得器件阈值电压负向漂移。随后的TDDB测试表明,与中子辐射一致,总剂量辐射未改变栅漏电演化形式,但氧化层击穿时间提前。这是总剂量辐射在氧化层内引入额外空穴陷阱和中性电子陷阱的缘故。     

Vg=Vd/2应力模式下宽度变窄对HALO-pMOSFETs退化的影响

讨论了最差应力模式下(Vg=Vd/2)宽沟和窄沟器件的退化特性.随着器件沟道宽度降低可以观察到宽度增强的器件退化.不同沟道宽度pMOSFETs的主要退化机制是界面态产生.沟道增强的器件退化是由于沟道宽度增强的碰撞电离率.通过分析电流拥挤效应,阈值电压随沟道宽度的变化,速度饱和区特征长度的变化和HALO结构串联阻抗这些可能原因,得出沟道宽度增强的热载流子退化是由宽度降低导致器件阈值电压和串联阻抗降低的共同作用引起的.     

栅长对深亚微米器件总剂量辐射诱生漏电流的影响研究

对0.18 um 工艺NMOSFET器件进行总剂量辐照实验,包括不同栅长器件。由于深亚微米器件栅氧化层厚度较薄,对总剂量辐照不敏感,辐照前后器件阈值电压基本不发生变化。所有尺寸器件的关态漏电流随总剂量增加而增加。我们认为,总剂量辐射在浅沟槽隔离氧化物侧壁诱生成源漏之间漏电路径。该漏电路径是由于浅沟槽隔离氧化物种陷阱正电荷形成的。研究发现,辐射诱生的漏电流大小与器件栅长密切相关。通过主晶体管和寄生晶体管模型可以很好解释该现象。     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

关态应力下 P- MOSFETs的退化

研究了沟长从 0 .5 2 5 μm到 1.0 2 5 μm9nm厚的 P- MOSFETs在关态应力 ( Vgs=0 ,Vds<0 )下的热载流子效应 .讨论了开态和关态应力 .结果发现由于在漏端附近存在电荷注入 ,关态漏电流在较高的应力后会减小 .但是低场应力后关态漏电流会增加 ,这是由于新生界面态的作用 .结果还发现开态饱和电流和阈值电压在关态应力后变化很明显 ,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响 .Idsat的退化可以用函数栅电流 ( Ig)乘以注入的栅氧化层电荷数 ( Qinj)的幂函数表达 .最后给出了基于 Idsat退化的寿命预测模型     

不同栅压应力下1.8V pMOS热载流子退化机理研究

本文详细研究了不同栅压应力下1.8V pMOS器件的热载流子退化机理.研究结果表明,随着栅压应力增加,电子注入机制逐渐转化为空穴注入机制,使得pMOS漏极饱和电流(I_dsat)、漏极线性电流(I_dlin)及阈值电压(V_th)等性能参数退化量逐渐增加,但在V_gs=90%*V_ds时,因为没有载流子注入栅氧层,使得退化趋势出现转折.此外,研究还发现,界面态位于耗尽区时对空穴迁移率的影响小于其位于非耗尽区时的影响,致使正向I_dsat退化小于反向I_dsat退化,然而,正反向I_dlin退化却相同,这是因为I_dlin状态下器件整个沟道区均处于非耗尽状态.     

A study of flicker noise in MOS transistors operated at room and liquid helium temperatures

A study of flicker noise in MOS transistors operated in the linear and non linear regions at room and liquid helium temperatures is proposed. Besides, a theoretical analysis of the drain current noise characteristics is developed in the framework of the mobility fluctuation model as well as of the carrier number fluctuation model. It is shown experimentally that a close correlation between the drain current spectral density and the transconductance squared dependencies with gate voltage (or drain current) and drain voltage is observed in our devices both at room and liquid helium temperatures. Therefore, it is concluded that the carrier number fluctuation model is not only applicable to MOS devices operated at room temperature but also at liquid helium temperature in ohmic and non ohmic regimes. In addition, peculiarities of the drain current noise related to the appearance of a kink effect at liquid helium temperature in the saturation current characteristics are also discussed.     

An engineering model for short-channel MOS devices

An engineering model for short-channel MOS devices which includes the effect of carrier drift velocity saturation is described. Based on a piecewise carrier drift velocity model, simplified expressions for the DC drain current I_D, the small signal transconductance g_m and the output conductance g _ds in the saturation region are derived. For a given gate voltage, the expressions depend only on the threshold voltage V _T and the dimensions of the device, whose desired values are normally known     

Reduced hot-electron effects in MOSFET's with an optimized LDD Structure

A comparison of device degradation due to hot-electron injection is made for conventional MOSFET's and lightly doped drain (LDD) structures. The studies indicate that, for an optimized LDD structure, critical device parameters, such as threshold voltage, transconductance, and linear and saturated current drives, show significantly reduced degradation when subjected to accelerated life testing. These results imply long-term stability for LDD devices used in VLSI circuits.     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Statistical Models for Hot Electron Degradation in Nano-Scaled MOSFET Devices

In a MOS structure, the generation of hot carrier interface states is a critical feature of the item's reliability. On the nano-scale, there are problems with degradation in transconductance, shift in threshold voltage, and decrease in drain current capability. Quantum mechanics has been used to relate this decrease to degradation, and device failure. Although the lifetime, and degradation of a device are typically used to characterize its reliability, in this paper we model the distribution of hot-electron activation energies, which has appeal because it exhibits a two-point discrete mixture of logistic distributions. The logistic mixture presents computational problems that are addressed in simulation.     

Analytical modelling of electrical characteristics in γ-irradiated power VDMOS transistors

This paper deals with an analysis of γ-irradiation effects on basic electrical characteristics of power VDMOS transistors operated in both linear and saturation regions. First, an analytical model that yields the drain current and transconductance dependencies on gate oxide charge density is developed. The experimental data are utilized to establish a direct relation between the absorbed irradiation dose and the corresponding effective density of gate oxide charges. The drain current and transconductance of VDMOS devices are then modelled as the functions of radiation dose. Finally, the results of modelling are compared with experimental data.     

Hot carrier induced degradation in mesa-isolated n-channel SOIMOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps     

Characteristics of enhancement/depletion (E/D) gate MOSFET fabricated using ion implantation

The E/D gate MOSFET, which has an enhancement and depletion mode region under the same gate, is fabricated by using ion implantation as a tool for shifting threshold voltage. Threshold voltage, transconductance and drain breakdown voltage are studied as functions of implantation dose up to 12 × 10¹² cm^?2.It is found that, at an appropriate dose, the transconductance of this device is determined solely by the channel length of the enhancement mode region, and is larger than that of a short channel MOSFET with a standard structure but with the same drain breakdown voltage. Moreover, the dependence of threshold voltage on substrate bias measured in this device is found less sensitive to the transconductance than that in the standard short channel MOSFET.     

60Co γ-rays irradiation effect in DC performance of AlGaN/GaN high electron mobility transistors

Unpassivated/passivated AlGaN/GaN high electron mobility transistors(HEMTs) were exposed to 1.25MeV60Co γ-rays at a dose of 1 Mrad(Si).The saturation drain current of the unpassivated devices decreased by 15%at 1 Mrad γ-dose,and the maximal transconductance decreased by 9.1% under the same condition;moreover,either forward or reverse gate bias current was significantly increased,while the threshold voltage is relatively unaffected.By sharp contrast,the passivated devices showed scarcely any change in saturation drain current and maximal transconductance at the same γ dose.Based on the differences between the passivated HEMTs and unpassivated HEMTs,adding the C-V measurement results,the obviously parameter degradation of the unpassivated AlGaN/GaN HEMTs is believed to be caused by the creation of electronegative surface state charges in source-gate spacer and gate-drain spacer at the low dose (1 Mrad).These results reveal that the passivation is effective in reducing the effects of surface state charges induced by the 60Co γ-rays irradiation.so the passivation is an effective reinforced approach.