An analytical model for self-limiting behavior of hot-carrierdegradation in 0.25 μm n-MOSFET's

Hot-carrier degradation of short-channel n-MOSFETs becomes saturated after reaching a certain threshold value. The physical mechanism for this self-limiting behavior is investigated. It is proposed that the hot-carrier-induced oxide trapped charge and interface states form a potential barrier that repels subsequent hot carriers from causing further damage and can lead to the saturation of device degradation. A physical model is developed on the basis of the analysis. The model is verified by experimental results and can be used for more accurate device reliability projection     

Simulation of hot-carrier induced MOS circuit degradation for VLSIreliability analysis

A new integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. This reliability simulation tool incorporates: (1) an accurate 1-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors; and (2) physical models for both fundamental device-degradation mechanisms (charge trapping and interface trap generation). Hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. A repetitive simulation scheme ensures accurate prediction of the circuit-level degradation process under dynamic operating conditions. The evolution of hot-carrier related damage in each device is automatically simulated at predetermined time intervals, instead of extrapolating the long-term degradation using only the initial simulation results. Thus, the gradual variation of dynamic stress conditions is accounted for during the long-term damage estimates     

Physically based comparison of hot-carrier-induced andionizing-radiation-induced degradation in BJTs

A physically based comparison between hot-carrier and ionizing radiation stress in BJTs is presented. Although both types of stress lead to qualitatively similar changes in the current gain of the device, the physical mechanisms responsible for the degradation are quite different. In the case of hot-carrier stress the damage is localized near the emitter-base junction, which causes the excess base current to have an ideality factor of two. For ionizing radiation stress, the damage occurs along all oxide-silicon interfaces, which causes the excess base current to have an ideality factor between one and two for low total doses of ionizing radiation, but an ideality factor of two for large total doses. The different physical mechanisms that apply for each type of stress imply that improvement in resistance to one type of stress does not necessarily imply improvement in resistance to the other type of stress. Based on the physical model, implications for correlating and comparing hot-carrier-induced and ionizing-radiation-induced damage are discussed     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

Novel degradation effects in dynamically stressed p-channel MOSFETs

The hot carrier degradation of p-channel MOS transistors under dynamic operation modes is studied. Dynamic degradation of submicrometer transistors is compared with the results of conventional static stressing. The application of inverter-like waveforms to the devices under test allows the identification of anomalous degradation modes, which are not consistent with the usually reported hot-carrier-induced punch-through in p-channel transistors. A simple model for the interpretation of the observed effects is presented. The implications of the experimental results for a correct characterization of hot-carrier damage and device lifetime prediction are discussed     

SOI NLIGBT热载流子效应研究

SOI NLIGBT中热载流子效应分别通过直流电压的应力测试、TCAD仿真和电荷泵测试三种方法进行了研究。其中,不同直流电压应力条件下测得的衬底电流Isub和导通电阻Ron用来评估因热载流子效应引起的器件退化程度。为了进行理论分析,对器件内部的电场强度和碰撞离化率也进行了仿真。测试得到的电荷泵电流直接验证了器件表面的损伤程度。最后讨论了SOI LIGBT在不同栅压条件下的退化机制。     

Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs

The charge-pumping measurement technique was successfully applied to submicron (L_eff = 0.35 μm) n-MOSFETs on ultra-thin (50 nm) SOI film. The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces. We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation. Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface. The buried-oxide interface charging contributes less than 5% of the overall drain current degradation.     

A compact pre- and post-stress I-V model for submicrometerburied-channel pMOSFETs

In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data     

脉冲应力增强的NMOSFET's热载流子效应研究

 本文研究了交流应力下的热载流子效应,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET's的退化产生的影响.在脉冲应力下,阈值电压和跨导的退化增强.NMOSFET's在热空穴注入后,热电子随后注入时,会有大的退化量,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释.本文还定量分析研究了NMOSFET's退化与脉冲延迟时间和脉冲频率的关系,并且给出了详细的解释.在脉冲应力条件下,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果.     

通过直接栅电流测量研究PMOSFET's热载流子损伤

通过直接栅电流测量方法研究了热载流子退化和高栅压退火过程中PMOSFET's热载流子损伤的生长规律.由此,给出了热载流子引起PMOSFET's器件参数退化的准确物理解释.并证明了直接栅电流测量是一种很好的研究器件损伤生长和器件参数退化的实验方法.     

Hot carrier-induced SOI MOSFET degradation under AC stressconditions

The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested     

Investigation on hot-carrier-induced degradation of SOI NLIGBT

The hot-carrier-induced (HCI) degradations of silicon-on-insulator (SOI) lateral insulated gate N-type bipolar transistor (NLIGBT) are investigated in detail by DC voltage stress experiment, TCAD simulation and charge pumping test. The substrate current I_sub and on-state resistance Ron at different voltage stress conditions are measured to assess the HCI effect on device performance. The electric field and impact ionization rate are simulated to assist in providing better physical insights. And charge pumping current is measured to determinate the front-gate interface states density directly. The degradation mechanisms under different gate voltage stress conditions are then presented and summarized.     

Temperature dependence of hot-carrier-induced degradation in 0.1μm SOI nMOSFETs with thin oxide

This letter investigates hot-carrier-induced degradation on 0.1 μm partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

A new method for characterizing the spatial distributions ofinterface states and oxide-trapped charges in LDD n-MOSFETs

Previous studies showed that simultaneous determination of the interface states (Nit) and oxide-trapped charges (Q_ox) in the vicinity of the drain side in MOS devices was rather difficult. A new technique which allows a consistent characterization of the spatial distributions of both hot-carrier-induced Nit and Q_ox is presented. Submicron LDD n-MOS devices were tested and charge pumping measurements were performed. The spatial distributions of both Nit and Q _ox have been justified by two-dimensional (2-D) device simulation of the I-V characteristics for devices before and after the stress. Comparison of the drain current characteristics between simulation and experiment shows very good agreement. Moreover, results show that fixed-oxide charge effect is less pronounced to the device degradation for the experimental LDD-type n-MOS devices     

On the bremsstrahlung origin of hot-carrier-induced photons insilicon devices

Spectrally resolved absolute measurements of hot-carrier-induced photon emission in silicon are reported. In order to avoid uncertainties in geometrical and physical parameters, the simplest conceivable device, an avalanching p-n junction, was used. A photon emission efficiency of 2.9×10⁵ photons with energy higher than 1.14 eV per carrier crossing the junction, independent of the lattice temperature down to 20 K, was measured. On the basis of these results the bremsstrahlung origin of the hot-carrier-induced light emission is critically reviewed     

The impact of NMOSFET hot-carrier degradation on CMOS analogsubcircuit performance

This study presents some of the first experimental data on the impact of NMOSFET hot-carrier-induced degradation on CMOS analog subcircuit performance. Because of circuit design requirements, most NMOSFET's used for analog applications are biased in the saturation region with a low gate-to-source voltage. Under such operating conditions, in addition to interface states, significant numbers of hole traps are also generated inside the gate oxide. Because acceptor-type interface states are mostly unoccupied in the saturation region, hole traps are found to have a much more significant impact on analog NMOSFET device performance. The hot-carrier-induced degradation of analog subcircuit performance is also found to be quite sensitive to the particular circuit design and operating conditions. Circuit performance and reliability tradeoffs are examined     

Physical characterization of hot-electron-induced MOSFETdegradation through an improved approach to the charge-pumping technique

The physical mechanisms which are involved in the hot-carrier-induced degradation of CMOS transistor are analyzed by means of an improved approach to the charge-pumping measurement technique. The proposed experimental procedure allows the simultaneous characterization of both interface-states generation and carrier trapping in the gate insulator. The analysis is extended to both static and dynamic degradation processes, whose differences and similarities are discussed     

Lateral distribution of hot-carrier-induced interface traps inMOSFETs

The spatial profiles of hot-carrier-induced interface traps in MOSFETs with abrupt arsenic junctions and oxide thickness of 10-38 nm are determined using charge pumping both in the conventional manner and with a modified constant-field approach. For the thinnest oxides the damage is highly localized in a very sharp peak that is located inside the drain at the point of maximum lateral electric field. In thicker oxides, the damage peak is broader and is shifted toward the edge of the drain junction. Two-dimensional device simulations using the measured profiles are in qualitative agreement with measured I-V characteristics after degradation. However, the magnitude of the predicted degradation is underestimated, suggesting that significant electron trapping occurs also     

A mobility model for submicrometer MOSFET simulations includinghot-carrier-induced device degradation

The model presented includes the quantum effects of electrons in the inversion layer proposed by S.A. Schwarz and S.E. Russek (1983) and the surface scattering effects due to the interfacial charges. By comparison with experimental data from scaled MOSFETs, the limitation of K. Yamaguchi's (1983) mobility model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. In addition, it is shown that the modeling of the screening effect of Coulomb scattering plays an important role in simulating the hot-carrier-induced MOSFET degradation. The model can predict the current-voltage characteristics within 5% accuracy for scaled MOSFETs down to 0.5-μm, as well as the degradation of electrical characteristics due to hot-carrier effects for submicrometer MOSFETs