共查询到19条相似文献,搜索用时 109 毫秒
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理论分析了MOSFET关态泄漏电流产生的物理机制,深入研究了栅氧化层厚度为1.4nm MOSFET传统关态下边缘直接隧穿栅泄漏现象.结果表明:边缘直接隧穿电流服从指数变化规律;传统关态下边缘直接隧穿对长沟道器件的影响大于短沟道器件;衬底反偏在一定程度上减小边缘直接隧穿泄漏电流. 相似文献
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超薄栅MOS结构恒压应力下的直接隧穿弛豫谱 总被引:1,自引:1,他引:0
随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 . 相似文献
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随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具. 相似文献
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对纳米MOSFET关断态的栅电流、漏电流和衬底电流进行了模拟,指出边缘直接隧穿电流(IEDT)远远大于传统的栅诱导泄漏电流(IGIDL)、亚阈区泄漏电流(ISUB)及带间隧穿电流(IBTBT)。对50 nm和90 nm MOSFET器件的Id-Vg特性进行了比较,发现在高Vdd下,关态泄漏电流(Ioff)随IEDT的增加而不断增大,并且器件尺寸越小,Ioff越大。高k栅介质能够减小IEDT,进而减小了Ioff,其中HfSiON、HfLaO可以使边缘隧穿电流减小2~5个数量级且边缘诱导的势垒降低(FIBL)效应很小。但当栅介质的k>25以后,由于FIBL效应,关态泄漏电流反而增大。 相似文献
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The direct tunneling current through ultra-thin gate dielectrics is modeled by calculating the transmission coefficient of an idealized potential barrier that is modified by the image force. A numerical solution to the Schrödinger equation shows that the barrier lowering induced by image-potential affects the tunneling current largely. An analytical expression for the current is obtained within the Wentel–Kramers–Brillouin approximation. The effects of image force on the direct tunneling current are found to increase with the applied voltage across oxide (Vox) and to decrease with the oxide thickness (Tox). 相似文献
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Jonghwan Lee Bosman G. Green K.R. Ladwig D. 《Electron Devices, IEEE Transactions on》2002,49(7):1232-1241
An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects 相似文献
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We investigate the validity of the assumption of neglecting carrier tunneling effects on the self-consistent electrostatic potential in calculating the direct tunneling gate current in deep submicron MOSFETs. A comparison between simulated and experimental results shows that for accurate modeling of direct tunneling current, tunneling effects on potential profile need to be considered. The relative error in gate current due to neglecting carrier tunneling is higher at higher gate voltages and increases with decreasing oxide thickness. We also study the direct tunneling gate current in MOSFETs with high-K gate dielectrics 相似文献
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The effects of transition region on direct tunneling and Fowler–Nordheim (FN) tunneling in ultrathin metal–oxide–semiconductor field transistors are investigated by numerical analysis. Direct tunneling current in ultrathin gate oxide is shown to increase with the width of transition region. The applied voltage across the oxide at the maximum and minimum of FN tunneling current oscillations is observed to increase with the width of the transition region, and its relative increase also strongly depends on the width. Furthermore, the amplitude of FN tunneling current oscillations descends with the width of transition region, however, its attenuation factor trends to increase with the width. Usually the amplitude and its attenuation factor decrease with the ordinal number of current oscillation increasing. So the effect of the transition region on FN tunneling current oscillations may be used to extract the information about the transition region. 相似文献
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Hsu B.-C. Chen K.-F. Lai C.-C. Lee S.W. Liu C.W. 《Electron Devices, IEEE Transactions on》2002,49(12):2204-2208
Two-dimensional (2-D) device simulation is used to investigate the tunneling current of metal ultra-thin-oxide silicon tunneling diodes with different oxide roughness. With the conformal nature of ultrathin oxide, the tunneling current density is simulated in both direct tunneling and Fowler-Nordheim (FN) tunneling regimes with different oxide roughness. The results show that oxide roughness dramatically enhances the tunneling current density and the 2-D electrical effect is responsible for this increment of tunneling current density. Furthermore, a set of devices with controlled oxide roughness is fabricated to verify the simulation results and our model qualitatively agrees with the experiment results. 相似文献
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Tahui Wang Nian-Kai Zous Chih-Chieh Yeh 《Electron Devices, IEEE Transactions on》2002,49(11):1910-1916
The transient behavior of hot hole (HH) stress-induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence t/sup -n/ with the power factor n about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time- and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a flash EEPROM cell is derived. Finally, the dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100 /spl Aring/ to 53 /spl Aring/, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT). 相似文献