超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .数值求解的结果表明 :镜像势引起的势垒降低对超薄栅 MOS直接隧穿电流有较大的影响 .利用 WKB近似方法 ,获得了镜像势对直接隧穿电流影响的定性表达式 .镜像势对直接隧穿电流的影响随着栅电压的减小而增大 ,但是随着栅氧化层厚度的减小而减小     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素．数值求解的结果表明：镜像势引起的势垒降低对超薄栅MOS直接隧穿电流有较大的影响．利用WKB近似方法,获得了镜像势对直接隧穿电流影响的定性表达式．镜像势对直接隧穿电流的影响随着栅电压的减小而增大,但是随着栅氧化层厚度的减小而减小．     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

用DTPDO研究超薄栅氧化层的诱生缺陷

应用直接隧道比例差分(DTPDO)谱技术研究了深亚微米MOS器件超薄栅氧化层的应力诱生缺陷。实验结果发现超薄栅氧化层直接隧道栅电流的比例差分谱存在明显的三个谱峰。这意味着在超薄栅氧化层退化的过程中有三种氧化层高场诱生缺陷共存。研究结果表明,三种缺陷的饱和缺陷密度均随着应力电压和应力温度的增加而增加。三种缺陷的特征产生时间常数与器件的实验温度、所加的应力电压和氧化层的失效时间相关。     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

Effect of strain-temperature stress on MOS structure with ultra-thin gate oxide

A method called strain-temperature stress was adopted in this work to improve the quality of ultra-thin oxide on both MOS(p) and MOS(n) capacitors. MOS structures were baked at 100 °C under externally applied mechanical stress. Reduced gate leakage current, reduced interface trap density (D_it), and improved time-dependent-dielectric-breakdown (TDDB) characteristics were observed after tensile-temperature stress treatment without increasing the oxide thickness. On the contrary, compressive-temperature stress resulted in a degraded performance of MOS capacitors. Consequently, the tensile-temperature stress method is suggested as a possible technique to enhance the ultra-thin oxide quality of MOS structure.     

Modeling study of ultrathin gate oxides using direct tunnelingcurrent and capacitance-voltage measurements in MOS devices

Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

Gate leakage reduction for scaled devices using transistor stacking

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L/sub eff/) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.     

Tunneling into interface states as reliability monitor for ultrathin oxides

This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable.     

Impact of gate direct tunneling current on circuit performance: asimulation study

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm⩽t_ox⩽1.5 nm, L_g=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V_dd static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices