Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

dc-Conduction mechanism in lanthanum–manganese oxide films grown on p-Si substrate

Thin films of (La–Mn) double oxide were prepared on p-Si substrates for electrical investigations. The samples have been characterised by X-ray fluorescence (XRF) and X-ray diffraction (XRD) methods. The XRF spectrum was used to determine the weight fraction ratio of Mn to La in the prepared samples. The XRD study shows the formation of grains of LaMnO₃ compound through a solid-state reaction for annealing at 800 °C. Samples used to study the electrical characteristics of the prepared films were constructed in form of a metal–oxide–Si MOS structures. Those MOS structures were characterised by the measuring their capacitance as a function of gate voltage C(V_g) in order to determine the oxide charge density Q_ox, the surface density of states D_it at the oxide/Si interface, and to extract the oxide voltage in terms of gate voltage. The extracted dielectric constant of the double oxide film is lower than that of pure La₂O₃ film and larger than that of pure Mn₂O₃ film, but the formation of LaMnO₃ grains by a solid-state reaction at 800 °C increases the relative permittivity to 11.5. These experimental conclusions might be useful to be used in the field of Si-oxide alternative technique. The leakage dc current density vs. oxide field J(E_ox) relationship for crystalline films follow the mechanism of Richardson–Schottky (RS), from which the field-lowering coefficient and the dynamic relative permittivity were determined. Nevertheless, the leakage current density measured in a temperature range of (293–363 K) was not controlled by the RS mechanism. It was observed that the temperature dependence of the leakage current in crystalline (La–Mn) oxide insulating films has metallic-like temperature behaviour, which might be important in the technical applications.     

Direct tunneling of electrons in Al-n+-Si-SiO2-n-Si structures under conditions of nonstationary depletion of the semiconductor surface of the majority charge carriers

Specific features of direct tunneling of electrons through an ultrathin (∼40 ?) oxide in metal-SiO₂-Si structures under nonstationary conditions of depletion of the semiconductor surface, in which case the potential relief in the insulator is only slightly perturbed by external electric fields, have been experimentally studied. Penetrability of the tunneling barrier is appreciably limited by a classically forbidden region in n-Si (this region is brought about by fixed negative charge in SiO₂). As the voltage drop across oxide is increased, the electrons localized within this oxide transfer to the semiconductor, which is accompanied by a drastic increase in the tunneling current. The values of coefficients linear rise in the logarithm of tunneling current as the voltage at the isolator is increased are determined from the experiment. These values are not consistent with the data calculated on the basis of a model of a rectangular barrier with parameters typical of “thick” oxides. It is shown that actual values of the effective mass are bound to be larger than 0.5m ₀, while the height of the barrier is bound to be lower than 3.1 eV.     

A Modelisation of the temperature dependence of the Fowler–Nordheim current in EEPROM memories

In this paper, we suggest a new computation method to simulate the temperature behavior of Fowler–Nordheim tunneling current through the oxide of an EEPROM cell based on surface potential evaluation with temperature dependence. The main idea of this paper is to simulate the tunneling current temperature dependence with only Si–SiO₂ barrier height and surface potential dependences with temperature. Parameters are experimentally extracted from large SOS capacitor measurements. So, final results of the programming window have shown comparing to simulations and measurements.     

Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (T_ox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with T_ox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.     

Ultra-thick gate oxides: charge generation and its impact on reliability

In this work, degradation and breakdown characteristics of ultra-thick gate oxides (T_ox: 50–150 nm) used in power MOS devices is investigated. Measurements indicate, that in addition to charge generation via Fowler–Nordheim tunneling, a second mechanism becomes dominant in ultra-thick gate oxides even at moderate electrical fields (i.e. 7–8 MV/cm). The results suggest, that impact ionization and related electron–hole pair creation by energetic electrons is responsible for the experimental observations. The impact of these results on the interpretation of lifetime extrapolations from accelerated tests will be discussed.     

Modeling of direct tunneling current through interfacial oxide and high-K gate stacks

In this paper, we present a computationally efficient model to calculate the direct tunneling current from an inverted p-type (1 0 0) Si substrate through interfacial SiO₂ and high-K gate stacks. This model consists of quantum mechanical calculations for the inversion layer charge density and a modified WKB approximation for the transmission probability. The modeled direct tunneling currents agree well with a self-consistent model and experimental data. For the same effective oxide thickness (EOT) of 2 nm, the direct tunneling current of a HfO₂ high-K dielectric (6.4 nm, K_f=25) overlaying a 1 nm thermal oxide is reduced by four orders of magnitude compared with a pure SiO₂ film at low gate voltages. The effects of interfacial oxide thickness, dielectric constant and barrier height on the direct tunneling current have also been studied as a function of gate voltages.     

Soft breakdown of MOS tunnel diodes with a spatially non-uniform oxide thickness

The effect of electric stress on the characteristics of Al/SiO₂/p⁺-Si MOS tunnel diodes (d_ox=2.5–3 nm) is studied. Along with the gradual current changes, superimposed by the soft-breakdown-related steps, a non-trivial abrupt decrease in current is also revealed during the constant voltage stress. The latter occurred predominately under high bias and may be considered as an unusual appearance of the same soft breakdown events. In case of substantial spatial oxide thickness deviation, this effect is important even if it occurs within a small area.     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Temperature dependence of the reverse current in Schottky barrier diodes

The temperature dependences of the current I in reverse-biased Al/SiO₂/n-Si, Al/SiO₂/n-GaAs and Al/n-GaAs (with the native oxide) structures are measured. It is established that these dependences all have the property that the thermal activation energy decreases with increasing applied voltage and that at higher voltages the plots of ln I versus 1/T deviate from straight lines. The results can be explained on the basis of the fact that the current through the barrier is due to electron tunneling from surface states into the conduction band of the semiconductor. The field intensity in the Schottky barrier and the density of surface electron states in the interfacial layer of the semiconductor are estimated by comparing the experimental results with a tunneling theory that takes into account the effect of the semiconductor lattice phonons on the tunneling probability. Fiz. Tekh. Poluprovodn. 32, 882–885 (July 1998)     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .数值求解的结果表明 :镜像势引起的势垒降低对超薄栅 MOS直接隧穿电流有较大的影响 .利用 WKB近似方法 ,获得了镜像势对直接隧穿电流影响的定性表达式 .镜像势对直接隧穿电流的影响随着栅电压的减小而增大 ,但是随着栅氧化层厚度的减小而减小     

Low frequency noise in thin gate oxide MOSFETs

Low frequency, 1/f, noise of the drain current, I_D, fluctuations was measured on a series of Si MOSFETs with the gate oxide thickness, t_ox, varied from 25 to 40 Å by steps of 5 Å. The salient point of this work is a demonstration that, at sufficiently low I_D intensities, a mean low noise level in the MOSFETs is reduced as the gate oxide becomes thinner. This is explained assuming that the noise originates from the electron capture/release on Si/SiO₂ interface/border traps. The flat band voltage fluctuations, observable as noise, are linked then to the oxide charge fluctuations by a factor, that is inversely proportional to the gate capacitance, C_ox, and thus proportional to t_ox. At higher I_D, the results are more complicated, as the access resistance noise is also involved. We provide an interpretation of the ensemble of the data and show that the noise analysis can furnish quantitative estimates of several device characteristics. Device degradation and its consequences for the low frequency noise at higher current levels are also discussed.     

A complementary molecular-model (including field and current) for TDDB in SiO2 dielectrics

A molecular physics-based complementary model, which includes both field and current, is introduced to help resolve the E versus 1/E TDDB model controversy that has existed for many years It is shown here that either TDDB model can be valid for certain specified field, temperature, and molecular bonding-energy ranges. For bond strengths < 3eV, the bond breakage rate is generally dominated by field-enhanced thermal processes at lower fields and elevated temperatures and the E-Model is valid. At higher fields, lower temperatures and higher bond strengths the bond breakage mechanism must be hole-catalyzed and the TDDB physics is described well by the 1/E - model.However, neither the simple E-model nor 1/E-model works well for oxide thickness below t_ox< 4 run where direct tunneling effects dominate.     

The effect of transition region on the direct tunneling current and Fowler–Nordheim tunneling current oscillations in ultrathin MOS structures

The effects of transition region on direct tunneling and Fowler–Nordheim (FN) tunneling in ultrathin metal–oxide–semiconductor field transistors are investigated by numerical analysis. Direct tunneling current in ultrathin gate oxide is shown to increase with the width of transition region. The applied voltage across the oxide at the maximum and minimum of FN tunneling current oscillations is observed to increase with the width of the transition region, and its relative increase also strongly depends on the width. Furthermore, the amplitude of FN tunneling current oscillations descends with the width of transition region, however, its attenuation factor trends to increase with the width. Usually the amplitude and its attenuation factor decrease with the ordinal number of current oscillation increasing. So the effect of the transition region on FN tunneling current oscillations may be used to extract the information about the transition region.     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

Nanoscale structural characteristics and electron field emission properties of transition metal–fullerene compound TiC60 films

Transition-metal compound TiC₆₀ thin films were grown by co-deposition from two separated sources of fullerene C₆₀ powder and titanium. Study of structural properties of the films, by Raman spectroscopy, atomic force microscopy, and scanning tunneling spectroscopy reveals that the films have a deformed C₆₀ structure with certain amount of sp³ bonds and a rough surface with a large number of nanoclusters. z–V tunnelling spectroscopic measurements suggest that several charge transport mechanisms are involved in as the tip penetrates into the thin film. Conventional field electron emission (FEE) measurements show a high emission current density of 10 mA/cm² and a low turn-on field less than 8 V/μm, with the field enhancement factors being 659 and 1947 for low-field region and high-field region, respectively. By exploiting STM tunneling spectroscopy, local FEE on nanometer scale has also been characterized in comparison with the conventional FEE. The respective field enhancement factors are estimated to be 99–355 for a gap varying from 36 to 6 nm. The enhanced FEE of TiC₆₀ thin films can be ascribed to structural variation of C₆₀ in the films and the electrical conducting paths formed by titanium nanocrystallites embedded in C₆₀ matrix.     

Carrier injection efficiency for the reliability study of 3.5–1.2 nm thick gate-oxide CMOS technologies

The hot carrier (HC) reliability has been investigated in MOSFETs with ultra-thin SiO₂ gate-oxide ranging from T_ox=3.5 to 1.2 nm and in high speed CMOS technologies in order to identify the worst-case of HC injections. Distinctions are obtained between the influence of the T_ox thinning and the shrink of the gate-length with L_G ranging from 0.25 to 0.1 μm. Results show that the worst-case of HC damage can be different from the bias condition of the maximum substrate current (IB) in N-channel devices and of the hot electron (HE) injections in P-channel devices with the T_ox and L_G margin. It is shown that the interface trap generation (ΔN_it) has become the main damage mechanism at long term with the use of the correlation between charge pumping analysis and drain current reduction. We focus on the hole injection efficiency, the extension of the degraded region (ΔL) with the L_G reduction and the influence of the carrier energy which all participate to the degradation of ultra-thin gate-oxide MOSFETs submitted to carrier injections.     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

Definition of curve fitting parameter to study tunneling and trapping of electrons in Si/ultra-thin SiO2/metal structures

The tunneling of electrons through metal–oxide–silicon (MOS) structures with ultra-thin oxide is modeled using a linear model for the electron potential energy, an approach which simplifies the computation of both the interface potential and the field penetration distance in the substrate. The one-particle quantum problem is split into finding the metastable states induced by the internal field penetration in the substrate and the running states in the gate region. The two states are assumed to be connected by the condition for the continuity of the probability density at the substrate–dielectric interface. The electron probability current and the total gate current density are obtained for different gate voltages. As the model yields excellent fittings with experimental current–voltage (I–V) data for MOS structures, it was further applied to constant current stressing analysis in order to obtain values for important electron trapping parameters in the oxide. The resultant estimates of the electron trapping cross-section fall in the range of other independent determinations in the literature.