软件数字下变频技术研究

本文讨论了软件无线电接收机中数字下变频处理的高效算法和结构，其目的是在DSP中用软件完成数字下变频处理，这样可省去专用数字下变频器（DDC）硬件集成电路，并增强中频处理的灵活性，适应性，文中指出将混频、抽取、滤波结合在一起完成将大大减少运算量，并分析了将CIC滤波器与内插的二阶多项式滤波器组合进行有效抽取滤波的设计方案，仿真结果表明该方案有效可行。     

Application of filter sharpening to cascaded integrator-combdecimation filters

A new architecture for the implementation of high-order decimation filters is described. It combines the cascaded integrator-comb (CIC) multirate filter structure with filter sharpening techniques to improve the filter's passband response. This allows the first-stage CIC decimation filter to be followed by a fixed-coefficient second-stage filter, rather than a programmable filter, thereby achieving a significant hardware reduction over existing approaches. Furthermore, the use of fixed-coefficient filters in place of programmable-coefficient filters improves the overall throughput rate. The resulting architecture is well suited for single-chip VLSI implementation with very high data-sample rates. We discuss an example with specifications suitable for use in a wideband satellite communication subband tuner system and for signal analysis     

软件无线电数字中频处理的优化设计

软件无线电是目前通信领域研究的热点,其关键技术之一数字中频技术是多速率信号处理理论的典型应用。本文研究了窄带信号条件下,高倍抽取的数字下变频设计,重点分析了基于CIC滤波器和HB滤波器的多级抽取算法。经比较,该设计比单级多相抽取设计节省98.8％的资源,完全可在单片FPGA内实现,而且,滤波性能优于设计指标要求。     

基于多相结构和部分锐化的CIC抽取滤波器

该文将传统的CIC(Cascaded Integrator Comb)滤波器传递函数分解为递归和非递归部分,可独立调整两者的级联因子;对递归部分进行尖锐化处理改善滤波器的通带衰落,利用电路的等价交换性将抽取因子提前使其工作在低采样率;对非递归部分进行多相分解,实现高速滤波。计算机仿真表明:与传统的CIC、锐化CIC滤波器相比,改进的CIC具有好的通阻带特性;并从通带衰落和混叠抑制的角度,分析了递归和非递归部分的级联因子的取值对整个改进的CIC滤波器特性的影响。     

多速率采样中的CIC滤波器设计与分析

CIC滤波器是常用于多速率采样抽取或内插过程中的高效滤波器,具有结构简单,易于工程实现的特点。以提高采样速率为例,首先介绍了内插理论和CIC滤波器原理,重点给出了CIC滤波器设计方法,并分析了CIC滤波器级联级数和滤波器阶数的选取对通带衰减和旁瓣抑制的影响,仿真结果验证了设计方法的有效性和可行性。     

Design of Dual‐Mode Digital Down Converter for WCDMA and cdma2000

We propose an efficient digital IF down converter architecture for dual‐mode WCDMA/cdma2000 based on the concept of software defined radio. Multi‐rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual‐mode receiver for WCDMA and cdma2000. A sub‐sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi‐rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.     

Weighted median filters with sigma-delta modulation encoding

Digital decimation filters play a fundamental role in oversampled sigma-delta A/D decoders. In this paper, we first show that weighted median (WM) filtering of a demodulated sequence (at the Nyquist rate) can be implemented concurrently in the A/D decoder. Through a simple modification of the binary time-series outputted by the A/D modulator, the sequence obtained after the sigma-delta modulation (SDM) decoder is shown to be equivalent to WM filtering the multilevel sequence at the Nyquist rate. Second, we show that WM filters can be used for SDM decimation filters and that these filters are readily implemented in the SDM binary domain. A very promising characteristic of SDM converters equipped with WM decimating filters is that sharp discontinuities (edges) can be preserved and acquired. Thus, the bandlimited constraint imposed on the input signals can be relaxed making SDM more attractive to A/D conversion of signals containing sharp transitions. The proposed signal processing algorithms, in essence, combine A/D sigma-delta converters and WM filters into a single programmable system     

A Fast FIR filtering technique for multirate filters

This paper presents a technique for applying Fast FIR Algorithms (FFAs) to interpolation and decimation filters. In the event that the prototype filter has a symmetric impulse response, it is shown that the subfilters which result from the application of the FFA will be jointly symmetric. This fact may be exploited in order to further reduce the computational complexity of the system. The effect of transposition upon the proposed structure is discussed, and it is shown that transposition yields a more economical structure in the case of a decimation filter. The computational complexity of the proposed schemes is shown to compare favorably with that of the standard parallel filtering approach.     

小抽取倍数的FIR高效实现

对采样信号进行抽取是软件无线电中的一个重要环节,小抽取率时通常使用有限冲击响应(FIR)滤波器.当FIR滤波器的阶数较高时,将会对信号处理的速度产生较大的影响.针对级联-积分-梳状(CIC)滤波器系数少且全为"1"的特点,提出了在小抽取率时采用单级CIC滤波器和FIR滤波器级联的方式来减少FIR滤波器的阶数,从理论上给出了FIR滤波器减少的阶数和CIC滤波器的阶数之间的关系.在此基础上,借助多相滤波结构还可进一步降低FIR滤波器阶数.计算机模拟验证了方法的有效性.     

FPGA应用中CIC抽取滤波器增益校正的实现

在中频数字化信号处理中,FPGA应用越来越广泛,DDC的FPGA模块化非常必要,CIC滤波器由于其结构只用到加法器和延迟器,很适合用FPGA来实现,通常工作在DDC系统中运算量大的第一级。本文分析了CIC滤波器的抽取原理、性能、影响参数及增益产生原因,针对实际应用中5级CIC滤波器在不同抽取率下对信号进行抽取时,所产生的增益问题,给出了校正方法,并在Modelsim仿真中得到了验证。     

一种基于CIC滤波器的有效锐化方法研究

介绍了对积分梳状滤波器（CIC滤波器）的有效锐化。所提出的锐化滤波器的结构由两个主要部分组成：一个梳状滤波器的级联部分和一个锐化滤波器部分。所提出的方案使得滤波器中锐化部分的工作速率比输入速率大为降低，其频谱响应特性比传统的也有所改进。通过MATLAB仿真，可看出改进锐化后的滤波器性能更优。     

级联COSINE滤波器在抽取滤波中的研究

为了解决高速抽取滤波器系统中传统CIC滤波器旁瓣抑制不够的问题,通过对级联COSINE抽取滤波器和传统CIC抽取滤波器的原理推导进行对比,分析出级联COSINE滤波器在幅频特性上同CIC滤波器具有很大相似之处,且在满足高速抽取滤波器的情况下,同时具备很好的低通特性和硬件实现性。通过MATLAB仿真实验得到,级联COSINE滤波器在进行32倍整数抽取时,第一旁瓣衰减约是传统CIC滤波器的2倍,进而说明相对于传统CIC滤波器,级联COSINE滤波器具有更好的旁瓣抑制性能。     

Reducing CIC filter complexity

This paper provides several tricks to reduce the complexity and enhance the usefulness of cascaded integrator-comb (CIC) filters. The first trick shows a way to reduce the number of adders and delay elements in a multi-stage CIC interpolation filter. The result is a multiplierless scheme that performs high-order linear interpolation using CIC filters. The second trick shows a way to eliminate the integrators from CIC decimation filters. The benefit is the elimination of unpleasant data word growth problems.     

Decimation schemes for /spl Sigma//spl Delta/ A/D converters based on Kaiser and Hamming sharpened filters

Cascaded-integrator-comb (CIC) filters are efficient anti-aliasing rate-conversion filters widely used for /spl Sigma//spl Delta/ A/D converters. High-order structures, attempting to increase the noise rejection within the folding bands, have the drawback of inserting multiple zeros in the same positions and increasing the edge-band attenuation. A combination of sharpened and CIC filters is proposed in the paper, with the goal of increasing the rejection of the /spl Sigma//spl Delta/ quantisation noise around the folding bands and reducing the pass-band drop of the designed decimation filters with respect to classic CIC structures. Design criteria, leading to optimised structures, and comparisons are given with respect to both classical and modified CIC filters.     

Two Classes of Frequency-Response Masking Linear-Phase FIR Filters for Interpolation and Decimation

This paper introduces two classes of frequency-response masking (FRM) linear-phase finite (length) impulse response (FIR) filters for interpolation and decimation by arbitrary integer factors M. As they are based on the FRM approach, the proposed filters are low-complexity (efficient) sharp-transition linear-phase FIR interpolation and decimation filters. Compared to previously existing FRM linear-phase FIR filter classes for interpolation and decimation, the new ones offer lower complexity and more freedom in selecting the locations of the passband and stopband edges. Furthermore, the proposed classes of FRM filters can, as special cases, realize efficient Mth-band FRM linear-phase FIR interpolation and decimation filters for all values of M. Previously, only half-band (M = 2) FRM linear-phase FIR filters have appeared in the literature. The paper includes design techniques suitable for the new filters and design examples illustrating their efficiency.     

DDC中的抽取滤波器设计及FPGA实现

本文介绍了在数字下变频（DDC）中的抽取滤波器系统设计方法和具体实现方案。采用CIC滤波器、HB滤波器、FIR滤波器三级级联的方式来降低采样率。通过实际验证，证明了设计的可行性。     

Cascade linear phase recursive half-band filters implement the most efficient digital down converter

The digital down converter (DDC) is a fundamental component in modern DSP based receivers. The basic architecture is the DSP implementation of the Edwin Armstrong heterodyne circuit. It is formed by three processes, a quadrature heterodyne, a pair of low-pass filters, and an M-to-1 down sampler. The index M is the ratio of input to output bandwidth of the filtering process. When M is large, the filtering is often performed in two sub-filters: a cascade integrator comb (CIC) filter that performs most of the down sampling followed by a pair of half-band filters that perform spectral correction, some final bandwidth reduction, and the remainder of the down-sampling. The attraction of the CIC filter is that it performs the filtering without multiplies. In this paper we present two alternate filter structures that offer significant computational advantages over the conventional CIC based DDC. These architectures offer the minimum power implementation of a DDC and likely will find great value in battery operated radio receivers.     

Two-stage CIC-based decimator with improved characteristics

A simple two-stage multiplierless cascaded-integrator-comb (CIC)-based decimator is presented. The first stage is a cascaded CIC filter whereas the second stage is a cascaded CIC filter and a second-order multiplierless compensator. The proposed decimator can be realised without filtering at high input rate by making use of the polyphase decomposition of the comb filter in the first stage. The proposed filter exhibits high aliasing attenuation and a low passband droop. The design parameters are the decimation factors, M ₁ and M ₂, numbers of cascaded CIC filters L and K, and parameter b of the compensator.     

一种Σ-Δ A/D转换器抽取滤波器的设计

设计了一种Σ-ΔA/D转换器中的数字抽取滤波器。该滤波器应用于音频范围,采用多级多采样率的结构,由梳状滤波器、补偿滤波器以及两个半带滤波器组成。滤波器系数用标准符号编码实现,减少了乘法单元的使用。采用Simulink模拟过采样128倍的4位调制器输出;用Verilog编写用于测试的滤波器代码。在Matlab中分析滤波器输出码流,得到的信噪比为101 dB,能够满足高端音频A/D转换器的要求。     

Polyphase FIR Networks Based on Frequency Sampling for Multirate DSP Applications

It is well known that the frequency sampling approach to the design of Finite Impulse Response digital filters allows recursive implementations which are computationally efficient when most of the frequency samples are integers, powers of 2 or null. The design and implementation of decimation (or interpolation) filters using this approach is studied herein. Firstly, a procedure is described which optimizes the tradeoff between the stopband energy and the deviation of the passband from the ideal filter. The search space is limited to a small number of samples (in the transition band), imposing the condition that the resulting filter have a large number of zeros in the stopband. Secondly, three different structures to implement the decimation (or interpolation) filter are proposed. The implementation complexity, i.e., the number of multiplications and additions per input sample, are derived for each structure. The results show that, without taking into account finite word-length effects, the most efficient implementation depends on the filter length to decimation (or interpolation) ratio.