FPGA应用中CIC抽取滤波器增益校正的实现

在中频数字化信号处理中，FPGA应用越来越广泛，DDC的FPGA模块化非常必要，CIC滤波器由于其结构只用到加法器和延迟器，很适合用FPGA来实现，通常工作在DDC系统中运算量大的第一级。本文分析了CIC滤波器的抽取原理、性能、影响参数及增益产生原因，针对实际应用中5级CIC滤波器在不同抽取率下对信号进行抽取时，所产生的增益问题，给出了校正方法，并在Modelsim仿真中得到了验证。

The Realization of CIC Decimation Filter Gain Correction in the Application of FPGA

In IF digital signal processing, FPGAs have been used more widely. DDC FPGA modular is necessary . Since its structure uses only adders and delayers, a CIC filter is achieved suitable for FPGA. CIC filters usually work in the first level with large amount of computation in DDC system. This article first analyses the theory, performance, impact parameters and gain generation reason of the CIC filter, for the problem that gain generated when five stages CIC decimation filter works under different decimation rates in practical application, and gives the method of gain correction, also has been verified in Modelsim Simulation.