A CMOS temperature-independent current reference optimized for mixed-signal applications

A low-drift, high PSRR and high-accuracy CMOS temperature-independent current reference, optimized for mixed-signal applications is presented. The topology is based on bootstrap current references that present a PSRR up to 60 dB, which is required for the proposed applications since they employ circuits where high-frequency switching noise is present. The proposed approach was successfully verified in a standard CMOS 0.35 μm process. The electrical simulations and laboratory measurements confirm that for a power supply between 2.7 V and 3.6 V and temperatures between −40 °C to 80 °C range, the proposed current reference exhibits an accuracy of ±0.5% and a mean relative temperature dependency of 62.5 ppm/°C.     

Analysis and improvement of PSRR in an envelope‐tracking power amplifier using a common‐drain amplifier topology

A common‐drain power amplifier (PA) for envelope tracking systems is presented. In envelope tracking, the main PA operates mostly in compression and the power supply rejection ratio (PSRR) is not high. Furthermore, the output noise of the supply modulator can be mixed with the RF signal and generates out‐of‐band emissions. In this article, instead of using a common‐source topology, the PSRR of the envelope tracking PA is inherently improved by utilizing a common‐drain topology. A comprehensive analysis shows that the common‐drain topology is less sensitive to the supply noise, as compared to the conventional common‐source topology. The proposed common‐drain PA is implemented using a discrete LDMOS PD20010‐E RF transistor. Measurement results show that the PSRR of the proposed common‐drain PA is improved by up to 7 dB as compared to that of the common‐source PA. For a two‐tone input with 10 MHz bandwidth at the center frequency of 700 MHz, the power added efficiency (PAE) and IM3 of the envelope tracking common‐drain PA are 20% and ? 28 dBc, respectively, at an average output power of 33.4 dBm. The amplifier also shows a 12.4 dB power gain. Moreover, by utilizing the envelope tracking, the PAE is improved by more than 5%.     

一种用于PWM的基准电压源设计

基于传统带隙基准的原理,设计了一种用于脉宽调制器(PWM)的带隙基准电压源。该电路采用4μm双极型工艺设计,并且整个基准电压源受控制器内部欠压锁定信号控制,经Cadence Spectre仿真表明该电压源具有良好的温度特性,电源抑制比高,带负载能力强,可满足PWM控制器的应用需要。     

高电源抑制比带隙基准电压源的设计

提出一种采用0.25 μm CMOS工艺的低功耗、高电源抑制比、低温度系数的带隙基准电压源(BGR)设计.设计中,采用了共源共栅电流镜结构,运放的输出作为驱动的同时也作为自身电流源的驱动,并且实现了与绝对温度成正比(PTAT)温度补偿.使用Hspice对其进行仿真,在中芯国际标准0.25 μm CMOS工艺下,当温度变化范围在-25～125℃和电源电压变化范围为4.5～5.5 V时,输出基准电压具有9.3×10-6 V/℃的温度特性,Vref摆动小于0.12 mV,在低频时具有85 dB以上的电源电压抑制比(PSRR),整个电路消耗电源电流仅为20μA.     

一种具有高稳定性的带隙基准电路

针对基极-发射极电压与温度呈非线性关系的问题,设计了一种高阶温度补偿方法:通过在PTAT产生电路的基极引入一个小电阻,在基准电压中迭加一个温度的指数函数,以达到消除高次项的目的。针对电源电压变化的问题,在保留传统带隙基准反馈回路的基础上,提出了一种钳位互补补偿方法,通过稳定偏置电流来降低电源变化对基准的间接影响。文中给出了详细的分析和电路实现。该电路通过Hspice验证,温度系数仅为1.43 ppm/℃,并具有0.105 mV/V的电源抑制特性及直流PSRR=65 dB的高电源抑制比。     

一种带有软启动的精密CMOS带隙基准设计

提出了一种新颖的带有软启动的高精密CMOS带隙基准电压源。采用UMC的0.6μm2P2M标准CMOS工艺进行设计和仿真,HSPICE模拟表明该电路具有较高的精度和稳定性,带隙基准的输出电压为1.293 V,在1.5 V~4 V电源电压范围内基准随输入电压的最大偏移为0.27 mV,基准的最大静态电流约为19μA;在-40℃~120℃温度范围内,基准随温度的变化约为4.41 mV,产生的偏置电流基本上不受电源电压的影响,而与温度成线性关系;在电源电压为3 V时,基准的总电流约为14.25μA,功耗约为42.74μW;并且基准具有较高的电源抑制比和较低的噪声(小于500 nV/Hz1/2),基准的输出启动时间约为25μs。     

高电源抑制比低温漂带隙基准源设计

设计并实现了一种新的高PSRR、低TC带隙基准源。重点研究了带隙基准源电源抑制能力,尤其是高频PSRR,达到宽频带范围PSRR高性能指标。采用0.35μm BiCMOS工艺进行仿真,结果表明,PSRR在1 Hz频率下达-108.5 dB,在15 MHz频率下达-58.9 dB;采用二次温漂补偿电路使得带隙基准源常温下输出参考电压1.183 V,在-40℃⁹5℃温度范围内,温漂系数低达1.5 ppm/℃。     

一种发动机高温差环境下的基准电压源电路

根据汽车发动机控制芯片的工作环境,针对常见的温度失效问题,提出了一种应用在发动机控制芯片中的带隙基准电压源电路。该电路采用0．181．LmCMOS工艺,采用电流型带隙基准电压源结构,具有适应低电源电压、电源抑制比高的特点。同时还提出一种使用不同温度系数的电阻进行高阶补偿的方法,实现了较宽温度范围内的低温度系数。仿真结果表明,该带隙基准电路在一50℃～＋125℃的温度范围内,实现平均输出电压误差仅5．2ppm／℃,可用于要求极端严格的发动机温度环境。该电路电源共模抑制比最大为99dB,可以有效缓解由发动机在

Abstract：

The paper presents a bandgap reference power source, which is designed to accommodate the wide range temperature environment for engine control modules and to avoid circuit invalidation caused by temperature. The bandgap reference based on current summing     

一种新型的BiCMOS带隙基准电压源

在分析传统带隙基准结构的基础上,根据当前集成电路设计中对基准电源的低压、低功耗、高电源抑制比的要求,设计了一种结构比较新颖的基准电压源电路。该电路工作在电流模式,带有启动电路和电流补偿电路,静态电流约为10μA,具有较低的温度系数和较高的电源抑制比。     

分段线性补偿型CMOS带隙基准电压源设计

设计了一种高精度CMOS带隙基准电压源电路.电路采用了共源共栅电流镜和自偏置技术,通过运放的负反馈分别获得正温度系数的电流IPTAT和负温度系数的电流ICTAT,通过电流的减法运算将在整个温度范围内分两段产生不同的补偿电流INL,并完成对带隙基准电压的分段线性补偿,由此得到温度系数很小的带隙基准电压.