Smith圆图辅助设计低噪声宽频带放大器

接收微弱射频信号需要研究低噪声放大器的设计,文中在分析传统低噪声放大器设计的基础上引入对放大器匹配电路品质因数,扩宽放大器的频带;通过加入电流负反馈及在负载端并联电阻,提高放大器的稳定性、降低放大器驻波比,得到宽频带低噪声放大器的设计方法.仿真结果表明设计的放大器工作绝对稳定.     

低噪声放大器的网络设计研究

本文就设计低噪声放大器的方法进行了研究分析。首先对低噪声放大器的特点进行了介绍,还介绍了低噪声放大器的网络组成和性能指标,最后本文用网络匹配法来设计低噪声放大器,并应用Ansoft公司的Designer软件包通过模拟集成电路国家重点实验室高频双极晶体管模型进行了设计分析。这种应用SmithTool工具、通过网络匹配的方法来设计电路更加方便快捷,且能符合工业基本要求。     

可调窄带滤波器中低噪声放大器的优化设计

低噪声放大器(简称低噪放)是射频接收前端中的重要部件。设计性能优良的低噪声放大器能够极大的提高通信系统接收机灵敏度和通信质量。本文对微波放大电路的设计方法进行了探讨,并在ADS软件界面上进行了微波窄带滤波器低噪声放大器的优化设计。     

激光回波小信号宽带放大器设计

设计了一款激光回波小信号宽带低噪声放大器。选用低噪声、高带宽电流反馈型差分运算放大器THS4509,采用两级放大电路结构以获得较大的放大倍数,利用传输线变压器实现输出信号由双端到单端转换。为减小噪声,采用过渡带特性最好的椭圆低通滤波器滤除带外噪声。经实验验证,该放大器具有40 dB放大倍数、120 MHz带宽和小于10 mV(pp)的系统噪声,能对各种反射率条件下不同目标反射回的微弱激光小信号进行有效放大,较好地解决了远距离和低反射率目标物体测距问题,实际测试测距量程可达450 m。     

超宽带低噪声放大器反馈与匹配技术研究

针对宽带放大器平坦度低、宽带匹配性差等问题,从负反馈电路理论、超宽带匹配技术以及宽带电路和高频电路设计的器件选取等方面讨论了宽带低噪声放大器的设计。在ADS辅助下,设计了工作频段在0.2～3GHz超宽带低噪声放大器。通过优化电路元件各项参数,实现了30dB的高增益、±1.5dB平坦度、低于1.5dB的噪声系数、优于-10dB的输入输出回波损耗的目标。     

C波段低噪声放大器的设计

低噪声放大器(简称低噪放)是射频接收前端中的重要部件.一个性能良好的低噪声放大器可大大改善接收机的信噪比.本文介绍了一种C波段低噪声放大器的设计原理和设计方法,并给出了设计结果.该放大器采用NEC公司的NE3210S01场效应晶体管(FET),为达到较高的增益和较好的增益平坦度,采用两级级联的方式.输出端串联一个有耗元件(电阻)保证放大器的稳定性.利用ADS强大的仿真优化功能设计了输入、输出及级间匹配电路,最终制成的放大器经反复调试后在4.5 G～5.5 GHz范围内增益(25±0.7)dB,噪声系数小于1.3 dB,输出驻波小于1.5,达到了设计要求.     

射频宽带低噪声放大器设计

介绍了射频宽带放大器的设计原理及流程。设计实现的射频宽带低噪声放大器,采用分立器件和微带线匹配,选用Agilent公司生产的低噪声增强赝配高电子迁移率晶体管ATF-551M4,用ADS软件进行设计、仿真和优化,实现了在1.1GHz～2.2GHz范围内,增益24dB以上,噪声系数小于1.2dB的两级宽带低噪声放大器设计。由于设计频带覆盖了多个通信常用频点,因此决定此低噪声放大器的应用会十分广泛。最后利用ProtelDXP软件对电路进行了版图设计,并在FR4基板上实现了该设计,给出了实测结果。     

P波段低温低噪声放大器的设计与测量

本文介绍了用于P波段高温超导滤波系统的低温低噪声级联放大器的研制以及低温系统调谐方法和测试方法。低噪声放大器采用Agilent ATF-54143高电子迁移率场效应晶体管,集总参数元件进行设计,引入源级负反馈与有耗电阻提高稳定性,选用П型输入匹配网络,扩展带宽,满足直流偏置的要求。制备的低温低噪声放大器在70K温度下,工作频段为450-550MHz,两级放大电路噪声低于0.5dB,输入驻波比优于1.3,增益29.2±0.3dB。采用了两极供电系统以方便在70K的条件下对滤波系统进行调节,使得前级滤波器和低噪声放大器获得较好匹配,最终系统输入驻波比优于1.3,增益27±0.1dB,带宽15MHz,系统噪声小于0.6dB。     

用于WLAN的2.4GHZ低噪声放大器的设计与分析

本文基TSMC 0.25微米CM0S工艺,设计了一个应用于2.4GHZ ISM频段的低噪声放大器,电路采用电流复用技术的差分电路,应用inductive source degeneration方法实现LNA的输入阻抗为50 Q,从而和前级的滤波器实现最大的功率传输.设计结果:低噪声放大器的噪声(NF)达到1.2dB,功率增益为22 dB,线性度(ⅡP3)-8dBm,输入返回损耗(S11)-36.8dB,输出返回损耗(S22)-31.6dB.     

2～8GHz宽带低噪声放大器设计

文中利用负反馈和宽带匹配技术,结合计算机辅助设计,在2~8GHz的范围内实现了增益G=20±1dB,噪声系数≤3·5dB的宽带低噪声放大器。并对该类放大器的制作工艺做了简单介绍.该放大器工艺简单成本较低,可以推广使用.     

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

A fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.     

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The duplex current‐reused topology with equivalent three common‐source gain stages cascaded is utilized to fulfil the low‐power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk‐bias control is employed to improve the linearity performance with large‐signal swing and to extend the auxiliary transistors bias‐control range. The proposed LNA is fabricated in a 0.18‐um 1P5M complementary metal–oxide–semiconductor process and consumes a 3.13‐mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of −19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

0.03～4.5GHz超宽带低噪声放大器设计与实现

采用负反馈和均衡器结构,选用Avago公司生产的增强型高电子迁移率晶体管ATF55143,利用ADS软件设计、仿真和优化,最终实现了一款覆盖0.03~4.5 GHz频段的低噪声放大器,该模块中的低噪声放大器使用分立元件搭建,匹配电路调试灵活,满足了模块对输入输出驻波的高要求。其增益大于25 d B,平坦度小于等于±0.9 d B,噪声系数小于1.2 d B,输入输出驻波比小于1.75。该放大器模块体积小巧,成本较低,调试灵活,可望在通讯领域得到广泛应用。     

A common‐gate common‐source low noise amplifier based RF front end with selective input impedance matching for blocker‐resilient receivers

This paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common‐gate common‐source LNA with capacitive feedback, together with an N‐path filtering load. The capacitive feedback across the LNA ensures that the selective N‐path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front‐end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28‐nm fully depleted silicon‐on‐insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11‐mA current from a 1‐V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out‐of‐band blocker compression point of ?1.5 dBm and out‐of‐band IIP3 of +14 dBm at a 100‐MHz offset from LO frequency. In comparison with a traditional common‐gate common‐source LNA‐based front end with wideband input impedance matching, the proposed front end achieves 3.5‐dB improvement in the blocker compression point at a 100‐MHz offset from LO.     

Effects of hot-carrier stress on the performance of CMOS low-noise amplifiers

The effects of direct current (dc) hot-carrier stress on the characteristics of NMOSFETs and a fully integrated low-noise amplifier (LNA) made of NMOSFETs in an 0.18-/spl mu/m complementary MOS (CMOS) technology are investigated. The increase in threshold voltage and decrease in mobility caused by hot carriers lead to a drop in the biasing current of the transistors. These effects lead to a decrease in the transconductance and an increase of the output conductance of the device. No measurable change in the parasitic gate-source and gate-drain capacitances in the devices under test were observed due to hot carriers. In the LNA, the important effects caused by hot carriers were a drop of the power gain and an increase of the noise figure. A slight increase in the input and output matching S/sub 11/ and S/sub 22/, respectively, after hot-carrier stress was observed. The linearity parameter IIP3 of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the I-V characteristics of the transistors in the LNA at the particular operating point where the measurements were performed.     

0.5T小型关节MRI仪器中低噪声前置放大器的设计

设计了一个可用于0.5T 小型关节MRI仪器中的低噪声前置放大器,给出了一种低场MRI仪器中LNA制作的可行方案。放大器采用两级级联的形式,第1级采用高电子迁移率晶体管ATF 54143,第2级采用双极型达林顿管ADA 4743。经过测试,所制作放大器的性能指标达到了预定要求,性能良好。放大器的工作频段为18~23 MHz,中心频率处噪声系数NF≈0.6 dB,增益G≈40 dB,带内波动小于1 dB,输入驻波比VSWR≤1.5,输出驻波比VSWR≤1.5。     

定向耦合器反馈型短波低噪声高线性放大器设计

利用双极性晶体管采用定向耦合器负反馈的形式设计了一款适用于短波超宽带接收机的低噪声高线性放大器。负反馈技术拓展了动态范围以及增益平坦度,定向耦合器的低损耗以及隔离吸收对噪声和输入输出端的匹配有很大改善。该放大器射频应用频率是1.5~100MHz,覆盖了6个倍频程。测试结果表明:放大器增益13dBm,噪声低于2.7dB,输出三阶截点高于43dBm,1dB压缩点高于26dBm,,输出二阶截点高于80dBm。     

Base coupled differential amplifier: a new topology for RF integrated LNA

A new topology of bipolar low noise amplifier (LNA) for RF applications, named base coupled differential (BCD), is presented. The proposed approach is compared by simulation against most classical topologies. The BCD configuration has the key advantage to join an integrated matching on a single‐ended input with a differential output. This is done by using down‐bond wiring, so that no integrated inductors are needed. The main advantages of this new topology are a drastic area reduction and an increased linearity range (or a reduced biasing current with the same linearity) together with a noise figure (NF) and voltage supply reduction. Particularly, the BCD LNA presented in this paper has been designed for 2.44GHz frequency operation. It is characterized by a NF of 1.93dB, a voltage gain (Av) of 19.5dB, an input impedance of 50Ωa third Input‐referred Intercept Point (IIP3) of ‐7.25dBm and a dissipated power (PD) equal to 19mW. Copyright © 2003 John Wiley & Sons, Ltd.