A drain avalanche hot carrier lifetime model for n- and p-channel MOSFETs

A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as /spl tau/(I/sub d//W)/sup 2//spl prop/(I/sub sub//I/sub d/)/sup -m/. The formula is different from the conventional /spl tau/I/sub d//W-I/sub sub//I/sub d/ model in that the exponent of I/sub d//W is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical /spl tau/-I/sub sub//W model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.     

双平衡支路低噪声放大器的设计与测试

本文通过使用ADS软件平台,设计了一种双平衡支路低噪声放大器(LNA),并设计、加工了实验样板进行测试。双平衡支路LNA是通过在输入和输出端分别加入3dB耦合器对输入信号进行分流、合并来提高性能的。3dB耦合器和晶体管之间还要设计阻抗匹配网络以减小信号的衰减。仿真结果表明LNA完全满足系统要求的性能指标。而测试过程中,由于实验样板中的无源元件并非仿真中所用的品牌贴片元件(比如,松下、TDK的器件),所以元件的寄生效应引起的阻抗失配和LC谐振导致了系统的性能在一定程度上的下降,但总体仍基本满足要求。这些问题可以通过使用品牌元件和调节元件值来解决。     

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The duplex current‐reused topology with equivalent three common‐source gain stages cascaded is utilized to fulfil the low‐power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk‐bias control is employed to improve the linearity performance with large‐signal swing and to extend the auxiliary transistors bias‐control range. The proposed LNA is fabricated in a 0.18‐um 1P5M complementary metal–oxide–semiconductor process and consumes a 3.13‐mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of −19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

Physical investigation of trap-related effects in power HFETs and their reliability implications

This paper presents a detailed physical investigation of trapping effects in GaAs power HFETs. Two-dimensional numerical simulations, performed using a hydrodynamic model that includes impact ionization, are compared with experimental results of fresh as well as hot-carrier-stressed HFETs in order to gain insight of intertwined phenomena such as the kink in the dc output curves, the hot-carrier degradation of the drain current, and the impact-ionization-dominated reverse gate current. Thoroughly consistent results show that: 1) the kink effect is dominated by the traps at the source-gate recess surface; and 2) as far as the hot-carrier degradation is concerned, only a simultaneous increase of the trap density at the drain-gate recess surface and at the channel-buffer interface (again at the drain side of the channel) is able to account for the simultaneous decrease of the drain current and the increase of the impact-ionization-dominated reverse gate current.     

Hot carrier degradation of HfSiON gate dielectrics with TiN electrode

Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-/spl kappa/ gate stack devices are severe than the one in the SiO/sub 2//poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.     

Design for Reliability: The RF Power LDMOSFET

The design of lateral diffused MOSFETs operating under continuous peak power in RF communication applications is one of the most demanding among semiconductor applications. This paper discusses design parameters related to the optimum performance of the transistor and constraints introduced by the fabrication process in achieving them. Nonstandard processing steps include thick pad oxides, a sinker to connect source to the bottom substrate, metal silicided gates, a source shield over the drift region, and often gold metallization for improved electromigration. Additionally, the device requires careful optimization for control of hot-carrier-related bias drift. The impact of negative charge injection in the gate oxide is to degrade the power gain and at higher output power levels, the linearity. The difficulties in assessment of the true impact of hot carriers on these parameters via measurement are highlighted. The contribution of matching impedances and class of bias on hot-carrier degradation is extracted via modeling. A ldquodesign for reliabilityrdquo approach for this product is investigated with four designs of the drift region, evaluated in terms of transconductance, on-resistance, breakdown voltage, capacitance, and hot-carrier immunity. A second-generation source shield demonstrates a tradeoff via significant reduction of feedback capacitance at a cost to transconductance. A deep drift design shows optimization in terms of gain without compromise to the hot-carrier immunity. Recent advances made in terms of packaging and electromigration are reviewed.     

Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density

As device scaling for higher performance bipolar transistors continues, the operation current density increases as well. To investigate the reliability impact of the increased operation current density on Si-based bipolar transistors, an accelerated-current wafer-level stress was conducted on 120-GHz SiGe heterojunction bipolar transistors (HBTs), with stress current density up to as high as J/sub C/=34 mA//spl mu/m/sup 2/. With a novel projection technique based on accelerated-current stress, a current gain shift of less than /spl sim/15% after 10/sup 6/ h of operation is predicted at T=140/spl deg/C. Degradation mechanisms for the observed dc parameter shifts are discussed for various V/sub BE/ regions, and the separation of the current stress effect from the self-heating effect is made based on thermal resistance of the devices. Module-level stress results are shown to be consistent with wafer-level stress results. The results obtained in this work indicate that the high-speed SiGe HBTs employed for the stress are highly reliable for long-term operation at high operation current density.     

Safe Operating Area Considerations for Integrated Trench-Based Power Devices

This paper discusses the hot-carrier and electrical safe operating area (SOA) of trench-based integrated power devices. The hot-carrier SOA is determined by the avalanche current, exhibiting a maximum at intermediate drain voltage. The initial hot-carrier degradation is dependent on the crystal plane on which the gate oxide is grown. During hot-carrier stress, interface states are formed in the device's accumulation region. No channel degradation is observed. The electrical SOA of the trench-based MOS (TB-MOS) is much larger than a comparable lateral DMOS (LDMOS) or vertical DMOS (VDMOS). Even for 100-ns pulses, the TB-MOS exhibits electrothermal effects, contrary to LDMOS and VDMOS. Finally, the intrinsic gate oxide quality of the trench gate oxide is reported on. It is proven that the oxide time-dependent dielectric breakdown is determined by the thinnest oxide along the trench sidewall.      

The energy-driven paradigm of NMOSFET hot-carrier effects

As negative-MOSFET (NMOSFET) size and voltage are scaled down, the electron-energy distribution becomes increasingly dependent only on the applied bias, because of quasi-ballistic transport over the high-field region. A new paradigm, or underlying concept, of NMOSFET hot-carrier behavior is proposed here, in which the fundamental "driving force" is available energy, rather than peak lateral electric field, as it is in the lucky electron model (LEM). The new prediction of the energy-driven paradigm is that the bias dependence of the impact-ionization (II) rate and hot-carrier lifetime is, to the first order, given by the energy dependences of the II scattering rate S/sub II/(E) and an effective interface state generation (ISG) cross section S/sub IT/(E), whereas, under the LEM, these bias dependences are determined by the number of electrons with energy above the II and ISG "threshold energies." This approach allows an experimental determination of S/sub IT/.     

Hot-carrier reliability comparison for pMOSFETs with ultrathinsilicon-nitride and silicon-oxide gate dielectrics

The degradation of 100-nm effective channel length pMOS transistors with 14 Å equivalent oxide thickness Jet Vapor Deposition (JVD) Si₃N₄ gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concern. Hot-carrier reliability of 14 Å Si₃N₄ transistors is compared to reliability of 16 Å SiO₂ transistors     

Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors

Anomalous hot-carrier degradation phenomenon was observed in a 0.5-mum 12-V n-type drain-extended MOS transistors (N-DEMOS) with various n-type drain-drift (NDD) implant dosage. Under the same stress condition, the device with a higher NDD dosage produces a higher substrate current, a slightly higher transconductance degradation, but a lower ON-resistance (RON) degradation. Two degradation mechanisms are identified from the analysis of the electrical data and two-dimensional device simulations. The first mechanism is hot-electron injection in the accumulation region near the junction of the channel and accumulation regions. The second mechanism is hot-hole injection in the accumulation region near the spacer. This injection of hot holes creates a positive-charge trapping in the gate oxide, resulting in negative mirror charges in the accumulation region that reduces RON. The second mechanism is identified to account for the anomalous lower RON degradation     

Physics and Characterization of Various Hot-Carrier Degradation Modes in LDMOS by Using a Three-Region Charge-Pumping Technique

Degradation of lateral diffused MOS transistors in various hot-carrier stress modes is investigated. A novel three-region charge-pumping technique is proposed to characterize interface trap (N _it) and bulk oxide charge Q_ox creation in the channel and in the drift regions separately. The growth rates of N_it and Q_ox are extracted from the proposed method. A two-dimensional numerical device simulation is performed to gain insight into device degradation characteristics in different stress conditions. This paper shows that a maximum I_g stress causes the largest drain current and subthreshold slope degradation because of both N_it generation in the channel and Q_ox creation in the bird's beak region. The impact of oxide trap property and location on device electrical characteristics is analyzed from measurement and simulation     

Study of Electrical Stress Effect on SiGe HBT Low-Noise Amplifier Performance by Simulation

This paper investigates the hot-carrier-induced performance degradation in a cascode low-noise amplifier using SiGe heterojunction bipolar transistors. Changes in device characteristics due to accelerated hot-carrier stress are examined experimentally. The vertical bipolar inter-company (VBIC) model parameters extracted from measured device data before and after stress are used in Cadence SpectreRF simulation to evaluate the circuit performance degradation     

Hot carrier degradation and ESD in submicrometer CMOS technologies:how do they interact?

In this paper, the phenomenon of channel hot carrier (CHC) induced degradation in transistors and its relation to ESD reliability is reviewed. The principles of CHC and the tradeoff with ESD during technology development from channel/drain engineering, including consideration for mixed voltage designs, are discussed. Also, latent damage due to ESD-induced effects on CHC is considered. Finally, it is shown how the generation of hot carriers can help in the optimization of the performance of advanced ESD protection concepts     

Channel Hot-Carrier Degradation in Short-Channel Transistors With High- $k$/Metal Gate Stacks

Channel hot-carrier (CHC) degradation in nMOS transistors is studied for different $hbox{SiO}_{2}/hbox{HfSiON}$ dielectric stacks and compared to $hbox{SiO}_{2}$. We show that, independent of the gate dielectric, in short-channel transistors, the substrate current peak (used as a measure for the highest degradation) is at $V_{G} = V_{D}$, whereas for longer channels, the maximum peak is near $V_{G} = V_{D}/hbox{2}$. We demonstrate that this shift in the most damaging CHC condition is not caused by the presence of the high- $k$ layer but by short-channel effects. Furthermore, the CHC lifetime of short-channel transistors was evaluated at the most damaging condition $V_{G} = V_{D}$ , revealing sufficient reliability and even larger operating voltages for the high- $k$ stacks than for the $ hbox{SiO}_{2}$ reference.      

SRAM circuit-failure modeling and reliability simulation with SPICE

Based on some new accelerated lifetime models and failure equivalent circuit modeling techniques for the common semiconductor wear out mechanisms, simulation program with integrated circuit emphasis (SPICE) can be used to characterize CMOS VLSI circuit failure behaviors and perform reliability simulation. This paper used a simple SRAM circuit as an example to demonstrate how to apply SPICE to circuit reliability modeling, simulation, analysis, and design. The SRAM circuit, implemented with a commercial 0.25-/spl mu/m technology, consists of functional blocks of 1-bit six-transistor cell, precharge, read/write control, and sense amplifier. The SRAM operation sequence of "write 0, read 0, write 1, read 1" was first simulated in SPICE to obtain the terminal voltage and current stress profiles of each transistor. Then, normalized lifetimes of all transistors in terms of each failure mechanism were calculated with the corresponding accelerated lifetime models. These lifetime values were sorted to single out the most damaged transistors. Finally, the selected transistors were substituted with failure equivalent circuit models, and SPICE simulations were performed again to characterize the circuit performance, functionality, and failure behaviors. The simulation shows that the 0.25-/spl mu/m technology, hot-carrier injection (HCI), and time-dependent dielectric breakdown (TDDB) had significant effects on SRAM-cell stability and voltage-transfer characteristics, while negative bias temperature instability (NBTI) mainly degraded the cell transition speed when the cell state flipped. This illustrative SRAM simulation work proves that, with SPICE and the failure equivalent circuit models, circuit designers can better understand the damage effects of HCI/TDDB/NBTI on the circuit operation, quickly estimate the circuit lifetime, make appropriate performance/reliability tradeoffs, and formulate practical design guidelines to improve the circuit reliability.     

大电流高精度恒流源

为了满足在白光LED照明、蓄电池的快速充电器、电气触点微电阻测量、实验室等诸多领域对恒流源的需求,本文阐述了以单片机为控制核心,控制由运算放大器和复合型大功率晶体管构成的低成本恒流源系统的设计和制作.该系统由数控模块、恒流源模块、直流电源模块组成.通过键盘设定恒流源的给定电流值,经单片机运算处理后,由D/A输出高精度电压信号作为大电流线性恒流源的输入参考电压,达到数控恒流的目的.测试结果表明,本恒流源在20～2000 mA输出电流时,输出电流与给定值误差小于1 mA,纹波电流≤0.2 mA,控制精度较高,设计方法实用有效.     

Damage mechanisms in impact-ionization-induced mixed-mode reliability degradation of SiGe HBTs

A robust, time-dependent methodology is used to investigate impact-ionization-induced mixed-mode reliability stress (the simultaneous application of high J/sub E/ and high V/sub CB/) in advanced SiGe HBTs. We present comprehensive stress data on second-generation 120-GHz SiGe HBTs, and use specially designed test structures with variable emitter-to-shallow trench spacing to shed light on the resultant damage mechanisms. We also explore the impact of mixed-mode stress on low frequency noise, ac performance, high-temperature device characteristics, and employ two-dimensional calibrated MEDICI simulations using the hot carrier injection current technique to better understand the physical damage locations.     

Recovery of shifted MOS parameters induced by focused ion beam exposure

The effects of focused ion beam (FIB) exposure on MOS transistors within a circuit were examined. It was found that FIB exposure does not cause parameter shifts as long as the gate is connected to the drain of other MOS transistors. However, the threshold voltage (V/sub t/) does shift during isolating the gate using a FIB. Further FIB exposure on MOS transistors with a floating gate is shown to cause larger shifts. Thermal annealing was studied to recover shifted V/sub t/. We demonstrated that a 400/spl deg/C-450/spl deg/C anneal could recover shifted V/sub t/ almost completely. Ninety percent recovery can be reached by annealing at 400/spl deg/C-450/spl deg/C for 1-2 hours, and V/sub t/ shifts can be reduced to about 10 mV.     

Improvement of aging simulation of electronic circuits using behavioral modeling

This paper presents an original method of analog circuits aging simulation. This method is based on a behavioral modelling of circuits that includes the effects of degradations on circuit parameters, on the basis of transistors aging. The efficiency of the method is demonstrated in the case of hot carriers degradation in an amplifier.