A 16 bit Stereo Audio ΣΔ A/D Converter

提出了一种16位立体声音频新型稳定的5阶∑△A/D转换器.该转换器由开关电容∑△调制器、抽取滤波器和带隙基准电路构成.提出了一种新的稳定高阶调制器的方法和一种新的梳状滤波器.采用0.5μm 5V CMOS工艺实现∑△A/D转换器.∑△A/D转换器可以得到96dB的峰值SNR,动态范围为96dB.整个芯片面积只有4.1mm×2.4mm,功耗为90mW.     

一种16位音频∑△ A/D转换器

提出了一种16位立体声音频新型稳定的5阶∑△A/D转换器.该转换器由开关电容∑△调制器、抽取滤波器和带隙基准电路构成.提出了一种新的稳定高阶调制器的方法和一种新的梳状滤波器.采用0.5μm 5V CMOS工艺实现∑△A/D转换器.∑△A/D转换器可以得到96dB的峰值SNR,动态范围为96dB.整个芯片面积只有4.1mm×2.4mm,功耗为90mW.     

集成过抽样∑-△A/D转换器设计研究

运用CMOS集成电路设计处理对象为语音信号的二阶∑-△A/D转换器.采用全差动设计、共模反馈电路和开关电容积分器实现二阶∑-△A/D转换器.     

一种3.3 V 9位50 MS/s CMOS流水线A/D转换器

设计了一种3.3 V 9位50 MS/s CMOS流水线A/D转换器。该A/D转换器电路采用1.5位/级,8级流水线结构。相邻级交替工作,各级产生的数据汇总至数字纠错电路,经数字纠错电路输出9位数字值。仿真结果表明,A/D转换器的输出有效位数(ENOB)为8.712位,信噪比(SNR)为54.624 dB,INL小于1 LSB,DNL小于0.6 LSB,芯片面积0.37 mm2,功耗仅为82 mW。     

一种CMOS IC片上电源ESD保护电路

随着集成电路工艺的高速发展,特征尺寸越来越小,静电放电对CMOS器件可靠性的危害也日益增大,ESD保护电路设计已经成为IC设计中的一个重要部分.讨论了两种常见的CMOS集成电路电源系统ESD保护电路,分析了它们的电路结构、工作原理和存在的问题,进而提出了一种改进的电源动态侦测ESD保护电路.使用HSPICE仿真验证了该电路工作的正确性,并且在一款自主芯片中使用,ESD测试通过士3000 V.     

一种16位音频ΣΔA/D转换器(英文)

提出了一种16位立体声音频新型稳定的5阶ΣΔA/D转换器.该转换器由开关电容ΣΔ调制器、抽取滤波器和带隙基准电路构成.提出了一种新的稳定高阶调制器的方法和一种新的梳状滤波器.采用0.5μm5V CMOS工艺实现ΣΔA/D转换器.ΣΔA/D转换器可以得到96dB的峰值SNR,动态范围为96dB.整个芯片面积只有4.1mm×2.4mm,功耗为90mW.     

一种CMOS新型ESD保护电路设计

金属氧化物半导体(MOS)器件的缩放技术使集成电路芯片面临着严重的静电放电(ESD)威胁,而目前采用的ESD保护电路由于电流集边效应等原因,普遍存在着抗静电能力有限、占用较大芯片面积等问题。根据全芯片ESD防护机理,基于SMIC 0.18μm工艺设计并实现了一种新型ESD保护电路,其具有结构简单、占用芯片面积小、抗ESD能力强等特点。对电路的测试结果表明,相对于相同尺寸栅极接地结构ESD保护电路,新型ESD保护电路在降低35%芯片面积的同时,抗ESD击穿电压提升了32%,能够有效保护芯片内部电路免受ESD造成的损伤和降低ESD保护电路的成本。     

多电源混合电压SoC的全芯片ESD设计实例

SoC是含有微处理器、外围电路等的超大规模集成电路,具有器件特征尺寸小、复杂度高、面积大、数模混合等特点,SoC的ESD设计成为设计师面临的一个新的设计挑战。文章详细介绍了一个复杂的多电源、混合电压专用SoC芯片的全芯片ESD设计方案,并结合电路特点仔细分析了SoC芯片ESD设计的难点,提出了先工艺、再器件、再电路三个层次的分析思路,并将芯片ESD总体解决方案中的关键设计重点进行了逐一分析,最后给出了全芯片ESD防护架构的示意图。该SoC芯片基于0.35μm 2P4M Polycide混合信号CMOS工艺流片,采用文中提出的全芯片ESD防护架构,使该芯片的HBM ESD等级达到了4kV。     

16级灰度320×240像素硅基有机发光驱动电路研究

使用华润上华（CSMC）0.5微米标准CMOS工艺实现了320×240像素硅基有机发光（OLED-on-Silicon）驱动电路。驱动电路集成了4位D/A转换器,实现16级灰度。提出了一种能够实现OLED微显示要求的极小电流驱动的3管电压控制型像素驱动电路。D/A转换器与像素驱动电路均以PMOS晶体管组成。OLED像素驱动中的传输门与电容器能够用来对D/A转换器的输出进行取样。在OLED像素驱动电路中加入一个额外的PMOS管,可以控制D/A转换器只驱动开启的一行,以降低芯片功耗。驱动电路可以正确的工作在50Hz帧频状态下,并给出了最终的电路版图。单个像素面积28.4μm×28.4μm,整个显示区域面积为10.7mm×8.0mm（对角线尺寸为0.52英寸）。测量的像素灰度电压波形表明驱动电路功能正确,测量芯片功耗为350mW左右。     

亚微米集成电路的ESD保护设计

介绍了一种带ESD瞬态检测的VDD-VSS之间的电压箝位结构,归纳了在设计全芯片ESD保护结构时需要注意的关键点;提出了一种亚微米集成电路全芯片ESD保护的设计方案,从实例中验证了亚微米集成电路的全芯片ESD保护设计.     

A 16×16 nonvolatile programmable analog vector-matrixmultiplier

In this paper, we present a 16×16 analog vector-matrix multiplier with analog electrically erasable and programmable read-only memories (EEPROMs) used as nonvolatile storage for the weight matrix values. Each weight matrix value is stored in an EEPROM transistor as a change of the threshold voltage, and the same EEPROM transistor is used for the multiplication by utilizing the square-law characteristic of the metal-oxide-semiconductor field-effect transistor. This allows a very simple circuit for the multiplier array with a size of about 1×1 mm². The vector-matrix multiplier has been fabricated in a 1,5-μm single-poly complementary metal-oxide-semiconductor/EEPROM technology and successfully tested     

16×16位高速低功耗并行乘法器的实现

基于0.6μm双阱CMOS工艺模型,实现了一种高速低功耗16×16位并行乘法器。采用传输管逻辑设计电路结构,获得了低功耗的电路性能。采用改进的低功耗、快速Booth编码电路结构和4-2压缩器电路结构,它在2.5V工作电压下,运算时间达到7.18ns,平均功耗(100MHz)为9.45mW。     

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.     

A 16-bit self-testing multiplier

A self-testing circuit is presented, i.e., a circuit able to signal out any inner fault. It is a 16-bit serial-parallel multiplier, based on a 2-bit Booth algorithm; data are coded in two's complement. The use of a rather cheap self-testing technique based on parity predicting results in the realization of a `self-testing-only' circuit requiring only about 25 percent extra silicon area. This realization permitted to study the feasibility of self-testing circuits. Critical points are also pointed out, such as the testing of I/O pins.     

A 16-bit LSI minicomputer

A 16-bit LSI minicomputer, using n-channel MOS technology, has been developed. The instruction set contains 126 instructions including floating-point arithmetic and is fully compatible with commercially available minicomputers such as the TOSBAC-40 and the Interdata 70. An execution speed of 2 /spl mu/s is obtained for register to register (RR) instructions. All the central processing unit (CPU) functions are implemented on a single board. An external microprogram ROM and short-single address microinstructions are used to realize high-system performance and reduce the chip area and the package pin numbers. Two LSI chips for the system, a single-chip processor, and a bit-sliced bus controller, are fabricated by a new n-channel MOS technology named the gate oxidation method (GOM) which provides a high-packing density, high speed, and a simplified process.     

A 16×16 crosspoint switch for ternary encoded signals

A crosspoint-switching chip that can switch bipolar, alternate mark inversion encoded (AMI) signals directly, is described. AMI encoding is a form of ternary, return-to-zero (RZ) coding where a binary zero is represented by an absence of a pulse and ones are represented with an alternating sequence of positive and negative pulses. Bipolar signals are used widely in interoffice telecommunications such as the T1, T1C, T2, and T3 digital transmission systems. The switching chip has 16 input and 16 output channels. Control of the chip allows any input to be connected to any output or outputs, providing a nonblocking connection. The architecture allows for expansion of the crosspoint array by paralleling several chips. The chip, fabricated using a standard 3-μm CMOS technology, is capable of handling data rates up to 15 Mb/s per channel, has about 17000 transistors, and has an area of about 32.5 mm²     

A low-power 16×16-b parallel multiplier utilizingpass-transistor logic

This paper describes a low-power 16×16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8 μm double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz     

A 16 bit/spl times/16 bit pipelined multiplier macrocell

A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfiguration of the basic array can be performed. The multiplier macrocell measures 1.7 mm/spl times/1.7 mm.     

A 6.75 ns 16×16 bit multiplier in single-level-metal CMOStechnology

A 16×16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has been optimized to balance the delays in different sections of the chip. A typical multiplication time of 6.75 ns at 3.3 V power supply has been measured, and better results are expected from a process optimized for 0.5 μm devices     

一种16×16位高速低功耗流水线乘法器的设计

提出了一种16×16位的高速低功耗流水线乘法器的设计。乘法器结构采用Booth编码和Wallace树,全加器单元是一种新型的准多米诺逻辑,其性能较普通CMOS逻辑全加器有很大改善。使用0.5μmCMOS工艺模型,HSPICE模拟结果表明,在频率为150MHz条件下,电源电压3.0V,其平均功耗为11.74mW,延迟为6.5ns。