自由空间全交叉微光学互连模块的研究

提出了一种新颖的自由空间微光学互连模块。该光学互连模块是由自由空间光学全交叉互连网络和非对称Ｆａｂｒｙ－Ｐｅｒｏｔ腔多量子阱反射调制器作为电寻址的四功能节点组成，具有稳定性好、体积小、重量轻、互连密度高、速度快、可编程等特点。     

光互连模块中位相型菲涅耳微透镜列阵的研制与应用

本文分析了位相型菲涅耳透镜的设计原理研制了四位相菲涅耳微镜列阵并应用于全交叉光互连网络模块中。制作的菲涅耳微透镜列阵具有单元尺寸小，占空比为１００％，焦距短，易于对准，光强分布均匀的优点，能够满足光互连网络小型化，集成化，模块化的需要。     

An efficient logic emulation system

The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGAs for logic. Several designs, including a 32-b CPU datapath, have been automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development, and special-purpose execution     

Modeling of optical devices for the design of multistage interconnection network systems

Guidelines of the modeling of an all-optical architecture is presented. This basic architecture is universal and flexible. It can be used as the switching building block for a number of interconnection networks. The power analysis of an all optical buffering architecture [1] that can be interfaced with such an element is discussed. The modeling analysis is given in terms of the switch model, the multistage model and the power analysis of the optical buffer. The architecture uses bistable optical devices such as Fabry-Perot etalons, SEED and S-SEED. A number of important issues remain to be addressed, such as the use of different nonlinear optical devices, synchronization, and simulation.     

Reliable and fast reconfigurable hierarchical interconnectionnetworks for linear WSI arrays

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Θ(log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated     

Multibeam planar arrays

The application of general N-port Butler matrices to the generation of multiple beams-from planar arrays is described. It is shown that the array must satisfy a "covering" condition. The interconnection of array and matrix is derived. The method, for determination of beam position is developed and applied to rectangular arrays to improve beam crossover level. Examples are presented.     

Free-space multistage optical interconnection networks using microlens arrays

Optical interconnections suitable for three-dimensional combining of lens arrays are presented. A multistage interconnection network with a self-routing function is described. The number of light paths this network is estimated to be capable of handling roughly ten or more times that of previously reported self-routing networks. Two separate lens arrays were fabricated to construct an 8×8 network of this design. The feasibility of the proposed interconnections was successfully demonstrated     

全交叉开关网络中四功能开关节点的实验研究

提出了一种基于全交叉开关网络的电寻址四功能多量子阱开关节点方式。采用２个１×８非对称Ｆａｂｒｙ－Ｐｅｒｏｔ胜多量子阱反射调制器列阵构成４对电寻址四功能多量子阱开关节点，实现了Ｎ＝８时全交叉开关网络第一级的开关结点功能，并给出了光学系统和实验结果。     

An area-efficient topology for VLSI implementation of Viterbidecoders and other shuffle-exchange type structures

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required for interconnection. The processing elements are implemented in pairs that are connected to form a ring. In this way three-quarters of the interconnections are between neighbors. The ring structure is laid out in two columns and the interconnection of nonneighbors is routed in the channel between the columns. The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2-μm CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V_DD=4.75 V and T_A=70°C). The core of the chip (excluding pad cells) is 7.8×5.1 mm² and contains approximately 50000 transistors. The interconnection network occupies 32% of the area     

Medium-Grain Cells for Reconfigurable DSP Hardware

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ldquoelementsrdquo, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 times 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays.     

CMOS／SEED光电子集成Crossbar互连网络的实现及控制

本文报道了光电子集成 Crossbar互连网络的光学实现及电控制方法。采用带光窗口的 CMOS/SEED灵巧像元列阵作为逻辑控制交换开关节点 ,输出光强的高低态对比度约为 1.4。由波长为 85 0 nm的半导体激光器发出的光束经过位相计算全息光栅分束器分束 ,形成 8× 2的光束阵列 ,为 CMOS/SEED光调制器窗口列阵提供泵浦光源 ,采用精密加工的高精度二维光纤阵列作为信号输入、输出接口器件。采用计算机并口产生电控制信号实现网络的交叉连接功能 ,编制了相应的控制软件。实验上完成了 16× 16 Crossbar光互连网络的交换功能     

Repeater using two wavelengths for passive optical star networks connection

A repeater for the 32 Mbit/s star-configured optical local area network (SOLARnet) has been developed. This repeater permits a tree-type interconnection of SOLARnets at layer 1 and enlarges the network scale. Wavelength-division multiplexing (WDM) is used to overcome self-collision (collision of the packet header with its packet).     

实时光学模糊关联记忆神经网络

构建了实时光学模糊关联记忆神经网络系统，采用空间面积编码实现了光学模糊逻辑，提出了分时处理技术，为实现更多神经元的网络提供了一条有效途径；并进一步论证了网络作为灵活实时互连功能模块的可行性；给出模拟运算和实验结果。     

A Novel Switched-Capacitor Based Field-Programmable Analog Array Architecture

A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).     

Public-key cryptography and open systems interconnection

The role of public-key cryptography in open systems interconnection (OSI) is discussed. A short tutorial introduction to public-key cryptography is followed by a discussion of how security fits into the OSI architecture, and what standards are being developed in this area. The use being made of public-key cryptography in the network layer and in the message handling system and directory application is also discussed     

Multiple quantum-well technology takes SEED

Progress in the development of self-electrooptic-effect devices (SEEDs) is discussed. The devices include the resistor-SEED (R-SEED) device, which can be viewed as a simple NOR gate. The symmetric SEED (S-SEED) and the logic-SEED (L-SEED) devices with improved features, functionality, and performance are also considered. The integration of FETs with multiple quantum well (MQW) modulators (FET-SEED), enables optical interconnections of electronic circuits. Where the SEED technology can be used is discussed, and an experimental optical switching fabric made using these devices is described     

S-SEED switching characteristics

S-SEED switching operation is studied, and an analysis technique introduced that produces a closed form expression relating the switching voltage to the input power contrast ratio and the responsivity characteristics of the device. A closed form equation for the switching time, and a general switching condition are derived as well. The analysis technique uses a single slope linear approximation to the responsivity curve, and is readily extended to a three epoch approach as well as an N-segment analysis scheme. Theoretical analysis is verified with a computer simulation using experimental data. A comprehensive model of the S-SEED with series and parallel resistors was also studied. It was found that the switching time could be reduced by as much as 24% over the purely capacitive model, and switching achieved with a minimum power ratio     

A mathematical programming method for constructing the shortest interconnection VLSI arrays

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.     

网络实用互连技术研究

从实际出发，在简单分析理论上的互连方案后，提出面向应用的互连概念，讨论现有的异步通信、Ｘ．２５网（如ＣＨＩＮＡＰＡＣ）与ＴＣＰ／ＩＰ网（如Ｉｎｔｅｒｎｅｔ）的互连技术，比较各种方案的优缺点。