Reliability modeling of Sn–Ag transient liquid phase die-bonds for high-power SiC devices

In this work, a novel foil-based transient liquid phase bonding process has been used to mount the SiC Schottky diodes. The Sn–Ag TLP interlayer material was produced in the form of preforms of multilayer foils, using electrochemical deposition. The foils were designed to keep the overall composition of Ag and Sn about 80% and 20% respectively. The optimized TLP bonding process parameters were used during the assembly process. The die-attachment characterizations revealed that resulting intermetallic compounds (Ag₃Sn and ζ) have melting point beyond 480 °C. The die-attachment produced low bending stresses, while heated from 30 °C to 400 °C. The reliability of Sn–Ag TLP bonded samples was studied during passive temperature cycling and during active power cycling. During power cycling, the crack rates were determined by measuring the crack lengths of the TLP bonded joints after failure. The failure criteria were set to be an increase of diode's forward voltage by 10% since the start of the power cycling tests. The thermo-mechanical simulations were performed to determine the damage parameter i.e. strain range amplitude ∆ ε_p. Based on mechanical characterization of the TLP bonded layers, a plastic material model was used. The crack propagation rates were modeled using Paris' Law. Based on comparisons with state-of-the-art silver sintering technique, it can be stated that the TLP bonding is a promising die-attachment technique and its power cycling reliability is similar to silver sintering.     

Joint reliability evaluation of thermo-compression bonded FPCB/RPCB joints under high temperature storage test

In this study, electrodes on a flexible printed circuit board (FPCB) and rigid printed circuit board (RPCB) were bonded by a thermo-compression bonding. Pb-free Sn–3.0Ag–0.5Cu solder was used as an interlayer. In order to determine the optimum bonding conditions for bonding pressure and time, a 90° peel test of the FPCB–RPCB joint was conducted. The relationships between the bonding conditions, interfacial reactions, and peel strength were investigated. The optimum bonding pressure and time were 2.04 MPa and 5 s at 260 °C, respectively. Thin and uniform (Ni,Cu)₃Sn₄ intermetallic compound (IMC) layers formed at both FPCB/Sn–3.0Ag–0.5Cu/RPCB interfaces. In a high temperature storage (HTS) test of 125 °C, the peel strength decreased as the aging time increased. After the HTS test, brittle interfaces formed in the PCB joints, resulting in the switching of the failure mode from a polyimide–electrode failure to a brittle IMC failure.     

Evaluation of solder joint reliability in flip-chip packages during accelerated testing

The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu₆Sn₅ intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains.     

Effects of Cu/Al intermetallic compound (IMC) on copper wire and aluminum pad bondability

Copper wire bonding is an alternative interconnection technology that serves as a viable, and cost saving alternative to gold wire bonding. Its excellent mechanical and electrical characteristics attract the high-speed, power management devices and fine-pitch applications. Copper wire bonding can be a potentially alternative interconnection technology along with flip chip interconnection. However, the growth of Cu/Al intermetallic compound (IMC) at the copper wire and aluminum interface can induce a mechanical failure and increase a potential contact resistance. In this study, the copper wire bonded chip samples were annealed at the temperature range from 150/spl deg/C to 300/spl deg/C for 2 to 250 h, respectively. The formation of Cu/Al IMC was observed and the activation energy of Cu/Al IMC growth was obtained from an Arrhenius plot (ln (growth rate) versus 1/T). The obtained activation energy was 26Kcal/mol and the behavior of IMC growth was very sensitive to the annealing temperature. To investigate the effects of IMC formation on the copper wire bondability on Al pad, ball shear tests were performed on annealed samples. For as-bonded samples, ball shear strength ranged from 240-260gf, and ball shear strength changed as a function of annealing times. For annealed samples, fracture mode changed from adhesive failure at Cu/Al interface to IMC layer or Cu wire itself. The IMC growth and the diffusion rate of aluminum and copper were closely related to failure mode changes. Micro-XRD was performed on fractured pads and balls to identify the phases of IMC and their effects on the ball bonding strength. From XRD results, it was confirmed that the major IMC was /spl gamma/-Cu/sub 9/Al/sub 4/ and it provided a strong bondability.     

Evaluation of stresses in packaged ICs by In situ measurements with an assembly test chip and simulation

Failures in ICs are more and more related to the whole packaging and less and less to the chip alone. The main problem comes from the mismatch between the different coefficients of thermal expansion which induces thermomechanical stresses and strain within the package. The authors present an assembly test chip (ATC) designed to evaluate thermomechanical stresses inside encapsulated integrated circuits. The experimental results are validated by finite-element simulation.     

Effects of Pd addition on Au stud bumps/Al pads interfacial reactions and bond reliability

The main purposes for developing low-alloyed Au bonding wires were to increase wire stiffness and to control the wire loop profile and heat-affected zone length. For these reasons, many alloying elements have been used for the various Au bonding wires. Although there have been many studies reported on wire strengthening mechanisms by adding alloying elements, few studies were performed on their effects on Au bonding wires and Al pad interfacial reactions. Palladium has been used as one of the important alloying elements of Au bonding wires. In this study, Au-1wt.%Pd wire was used to make Au stud bumps on Al pads, and effects of Pd on Au/Al interfacial reactions, at 150°C, 175°C, and 200°C for 0 to 1200 h thermal aging, were investigated. Cross-sectional scanning electron microscopy (SEM), energy-dispersive spectroscopy (EDS), and electron probe microanalysis (EMPA) were performed to identify intermetallic compound (IMC) phases and Pd behavior at the Au/Al bonding interface. According to experimental results, the dominant IMC was Au₅Al₂, and a Pd-rich layer was at the Au wire and Au-Al IMC. Moreover, Au-Al interfacial reactions were significantly affected by the Pd-rich layer. Finally, bump shear tests were performed to investigate the effects of Pd-rich layers on Au wire bond reliability, and there were three different failure modes. Cracks, accompanied with IMC growth, formed above a Pd-rich layer. Furthermore, in longer aging times, fracture occurred along the crack, which propagated from the edges of a bonding interface to the center along a Pd-rich layer.     

Modeling Fracture of Sn-Rich (Pb-Free) Solder Joints Under Mechanical Shock Conditions

With the increasing focus on developing environmentally benign electronic packages, lead-free solder alloys have received a great deal of attention. Mishandling of packages during manufacture, assembly, or by the user may cause solder joint failure. In this work, we conducted finite-element analysis to model solder joint fracture under dynamic loading conditions. The solder is modeled as a porous plastic material, and the intermetallic compound (IMC) material is characterized as an elastic material. The fracture of the solder is governed by void nucleation, and the IMC fracture is brittle in nature. The randomness of the void volume fraction in the solder and the defects in the IMC are considered and implemented in the finite-element package ABAQUS. The finite-element results show that the fracture mechanisms of the solder joints depend on the strain rate and IMC thickness. High strain rate and larger IMC thickness favor IMC-controlled fracture, which is brittle in nature. Low strain rate and smaller IMC thickness lead to solder-controlled fracture, which is governed by void growth and nucleation. Based on this finding, a mechanistic explanation for solder joint fracture is suggested.     

Comparison of Sn-Ag-Cu Solder Alloy Intermetallic Compound Growth Under Different Thermal Excursions for Fine-Pitch Flip-Chip Assemblies

The intermetallic compound (IMC) evolution in Cu pad/Sn-Ag-Cu solder interface and Sn-Ag-Cu solder/Ni pad interface was investigated using thermal shock experiments with 100-μm-pitch flip-chip assemblies. The experiments show that low standoff height of solder joints and high thermomechanical stress play a great role in the interfacial IMC microstructure evolution under thermal shock, and strong cross-reaction of pad metallurgies is evident in the intermetallic growth. Furthermore, by comparing the IMC growth during thermal aging and thermal shock, it was found that thermal shock accelerates IMC growth and that kinetic models based on thermal aging experiments underpredict IMC growth in thermal shock experiments. Therefore, new diffusion kinetic parameters were determined for the growth of (Cu,Ni)₆Sn₅ using thermal shock experiments, and the Cu diffusion coefficient through the IMC layer was calculated to be 0.2028 μm²/h under thermal shock. Finite-element models also show that the solder stresses are higher under thermal shock, which could explain why the IMC growth is faster and greater under thermal shock cycling as opposed to thermal aging.     

Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications

In the system-on-a-chip (SOC) era, chip layouts of integrated circuit (IC) products become more and more compact for cost reduction. To save layout area for SOC chips, on-chip electrostatic discharge (ESD) protection devices or input/output (I/O) transistors placed under bond pads is a good choice. To ensure that this choice is practicable, a test chip with large size NMOS devices placed under bond pads had been fabricated in a 0.35-/spl mu/m 1P4M 3.3-V CMOS process for verification. The bond pads of this test chip had been drawn with different layout patterns on the interlayer metals for two purposes. One is to investigate the efficiency against bonding stress applied on the active devices under the bond pads. The other purpose is to reduce the parasitic capacitance of bond pads for high-speed or high-frequency circuit applications. DC characteristics of these devices placed under bond pads had been measured under three conditions: before wire bonding, after wire bonding, and after thermal reliability stresses. After assembly with wire bond package and thermal reliability stresses, the measured results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied to save layout area of IC products by realizing on-chip ESD protection devices or I/O transistors under the bond pads, especially for the high-pin-count SOC.     

Parameter Modeling for Wafer Probe Test

This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact model is developed for the probe tip and wafer bond pad. Modeling results have shown that the probe test OT, probe tip shape and tip diameters, contact friction between the probe tip and bond pad, as well as the probe scrub of the probe tip on bond pad are important parameters that impact the failure of interlayer dielectric (ILD) layer under bond pad. Comparison between probe test damage and wire bonding failure shows the degree of damage to both probe test and wire bonding on the same bond pad structures. In addition that, a design of experiment (DOE) probe test with different ILD and metal thickness is carried. The correlation between the modeling and the DOE test is studied. The results show that the modeling solution agrees with the DOE probe test data. Modeling results have further revealed that probe test can induce the local tensile (or bending) first principal stress in ILD layer, which may be a root cause of the ILD failure in probe test.     

Reliability of nickel flip chip bumps with a tin-silver encapsulation on a copper/tin-silver substrate during the bonding process

This study focused on the feasibility of using Ni flip chip bumps with a Sn-2.5Ag (wt.%) solder encapsulation. The interfacial reaction and die shear property of the Ni flip chip bump with a Sn-Ag solder cap bonded on the electroplated Cu/Sn-Ag substrate were investigated with increasing bonding time. After bonding for 1 s (Cu_xNi_1−x)₆Sn₅ and Cu₆Sn₅ intermetallic compound (IMC) layers were formed at the upper and lower interfaces, respectively, with the former IMC being the predominant phase during bonding. The transformation of the solder cap into the (Cu_xNi_1−x)₆Sn₅ IMC depleted the solder after bonding for 30 s, and then the Ni concentration in the IMC gradually decreased with increasing bonding time. The shear property peaked after 30 s, and then decreased with increasing bonding time. The fractures occurred at the solder/Cu₆Sn₅ interface and inside the (Cu_x Ni_1−x)₆Sn₅ IMC after bonding for 1 s and 30 s, respectively, after which the fracture location shifted toward the (Ni_xCu_1−x)₃Sn₄/(Cu_x Ni_1−x)₆Sn₅ interface with increasing bonding time.     

金、铜丝球键合焊点的可靠性对比研究

金丝球焊是电子工业中应用最广泛的引线键合技术,但随着高密度封装的发展,铜丝球焊日益引起人们的关注。采用热压超声键合的方法,分别实现Au引线和Cu引线键合到Al-1%Si-0.5%Cu金属化焊盘。对焊点进行200℃老化实验的结果表明:铜丝球焊焊点的金属间化合物生长速率比金丝球焊焊点慢的多;铜丝球焊焊点具有比金丝球焊焊点更稳定的剪切断裂载荷,并且在一定的老化时间内铜丝球焊焊点表现出更好的力学性能;铜丝球焊焊点和金丝球焊焊点在老化后的失效模式不同。     

Electromigration studies of flip chip Sn95/Sb5 solder bumps on Cr/Cr-Cu/Cu under-bump metallization

The electromigration-induced failure of Sn95/Sb5 flip chip solder bumps was investigated. The failure of the joints was found at the cathode/chip side after current stressing with a density of 1×10⁴ A/cm² at 150°C for 13 sec. The growth of intermetallic compounds (IMCs) was observed at the anode side after current stressing. Voids were found near the current crowding area in the cathode/chip side, and the (Cu,Ni)₆Sn₅ IMC at the cathode/chip end was transformed into the Sn phase. The failure mechanism for Sn95/Sb5 flip chip solder joint is proposed in this paper.     

Interfacial thermal stresses in ACF bonding assembly

The interfacial stresses and chip cracking stress produced because of thermal and mechanical mismatch in layered electronic assembly are one of main reasons for the failure of electronic packages. The analytical model considering the nonlocal deformation of assembly was developed and applied to predict the interfacial stresses produced due to temperature variation for the short and long anisotropic conductive adhesive film (ACF) bonding assembly. The conditions of zero shear stress at the free ends and self-equilibrated peeling stresses were satisfied. Simultaneously the interfacial stresses of ACF assembly were also predicted by the corrected Suhir’s model, Wang’s model, Ghorbani’s model, local model and finite element model (FEM), which were compared with the results by the present model. In addition, the analytical expression of chip cracking stress was also obtained for layered electronic assembly. The approach is mathematically straightforward and can be extended to include the inelastic creep behavior.     

Electrical Resistance and Microstructural Changes of Silver–Epoxy Isotropic Conductive Adhesive Joints Under High Humidity and Heat

In this study, the degradation mechanism of chip resistors mounted with Ag–epoxy isotropic conductive adhesive (ICA) under two different environmental conditions, i.e., humidity exposure (85°C/85% relative humidity) and thermal cycling (TC, –40°C to 125°C), was examined by monitoring the change in electrical resistance and by transmission electron microscopy. The effect of the terminal finishes (Sn/Ni or Au/Ni) of the chip components on joint stability during those two tests was also examined. The electrical resistance of the Sn/Ni-plated chip component joined with Ag–epoxy ICA during both environmental tests increased with exposure time. On the other hand, the electrical resistance of the Au/Ni-plated chip component joined with Ag–epoxy ICA remained unchanged during both tests. In the case of the Sn/Ni-plated chip joint, Sn oxides such as SnO, SnO₂, and Sn-Cl-O were formed inhomogeneously on the surface of the Sn plating during the humidity exposure test. Under the TC test, microcracks were also observed at the Sn/epoxy and the Ag filler/epoxy interfaces. A Ni₃Sn intermetallic compound (IMC) was formed at the interface between Sn and Ni, and the Ni₃Sn₄ IMC was also formed at the Sn surface. In contrast, no oxide was found in the Au/Ni-plated chip joint during the humidity exposure test. Also, no IMC was found in that joint during the TC test. It is suggested that oxides, microcracks, and IMCs cause the electrical degradation of Sn/Ni-plated chip components joined with Ag–epoxy ICA.     

半导体器件金铝键合的寿命研究

金铝键合失效是MOSFET器件常见的失效模式之一,主要是由于金属间化合物的生成,影响了金铝键合的接触电性能,从而导致键合强度下降,接触电阻升高。针对这种失效模式,进行了三种不同高温条件下的加速寿命试验,并对这三种试验的器件进行金铝键合现象观察,对目前工艺水平下的金铝键合寿命进行了评估。     

Modeling of Thermally Induced Stresses in Three-Dimensional Bonded Integrated Circuit Wafers

A finite-element model has been developed to investigate the potential reliability issues of thermally induced stresses in interwafer Cu via structures in three-dimensional (3D) integrated circuit (IC) wafers. The model is first partially validated by comparing computed results against experimental data on via test structures from planar ICs. Computed von Mises stresses show that the predicted failure agrees with the results of thermal cycle experiments. The model is then employed to study thermal stresses in interwafer Cu vias in 3D bonded IC structures. The results illustrate that there is a concern regarding the stability of interwafer Cu vias. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch length at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing bonding thickness.     

Reliability and failure analysis of fine copper wire bonds encapsulated with commercial epoxy molding compound

The small outline transistor (SOT) devices which were interconnected with 20 μm copper bonding wire and encapsulated with commercial epoxy molding compound (EMC) have been used in a series of reliability tests which including the thermal shock test, the electrical service life test, and the isothermal aging test. Isolated IMC spots were found at the bonding interface during the thermal shock test. No void or crack was observed even after 1500 cycles thermal shock test. No electrical failure was happened. The isolated IMC spots also occurred at the Cu/Al bonds interface after 500 h electrical operation. After 1000 h electrical operation, the sizes of the IMC spots were about 0.5 μm. No layered IMC was observed. The IMCs were formed at the bonding interface when the aging temperature was between 150 °C and 250 °C. Micro cracks and Kirkendall voids were observed with the aging time of 9 days at 200 °C and the aging time of 9 h at 250 °C. The minor element in the EMC, Sb, has reacted with Cu wire and Cu bond surface at 250 °C when the aging time was more than 16 h. Cu₃Sb was the main product of the diffusion reaction. With the aging time of more than 49 h, the Cu wire was crashed into pieces and the Cu bond periphery has been severely corroded.     

随机振动载荷下板级焊点失效模式分析

通过搭建振动加速失效实验平台,完成了芯片中板级焊点的失效实验。在此基础上,对焊点进行电镜观察分析,以确定焊点在振动载荷下的失效模式。结果表明,内部焊点基本没有裂纹扩展迹象,裂纹集中于最外侧角的焊点,焊点的损伤程度分布从内至外呈递增趋势。裂纹的分布集中于PCB板侧和芯片侧的IMC层区域,即在焊点两侧的钎料疏松部位,并沿着IMC层区域的Cu₆Sn₅晶粒方向进行穿晶、沿晶扩展。裂纹的扩展接近于贯穿时,易发生瞬间脆性断裂。