CIS片上系统中伽玛校正的低功耗设计

为了实现CMOS图像传感器(CIS)片上系统(SoC)中伽玛(γ)校正的低功耗设计,同时又保证校正的精度,提出一种查找表和直线拟合相结合的γ校正技术。算法对灰度值较低的像素使用直接查找表方法校正,对于γ曲线上升缓慢部分的像素采用分段直线拟合的方法。在直线分段时,使用外层分段与内层分段相结合的方法,达到了分段优化的目的。算法保证了图像校正精度,与使用完全查找表法相比,误差在0.5 pixel之内。基于该方法设计了一个8 bit输入/8 bit输出的VLSI模块,通过FPGA对模块进行了验证,模块占用723个LE和195个LC寄存器,比完全查找表法减少了硬件资源耗费,实现了低功耗设计。系统最大工作频率可达148 MHz,完全满足实时处理的需求。     

自适应正弦数字滤波在微弱信号提取中的研究

针对强正弦干扰信号背景下微弱信号的提取提出一种新方法-自适应正弦滤波.自适应正弦滤波是将信号分解成不同频率信号的线性组合,按照最小均方误差准则自动调节各频率的权重以实现对实际信号的最佳逼近,利用算法收敛结果便可精确地得到所求信号的幅值和相位.MATLAB仿真结果证明,与数字相干检测法相比该方法能更快速地提取微弱信号.     

基于量化的LDPC译码算法的高效实现

论文提出了一种采用2维折线逼近的和积译码算法实现方案,避免了使用与量化比特数成指数关系增长的查找表,降低了译码器的存储器消耗。基于上述方案提出了一种次小值修正的最小和算法。该算法通过3个2维折线逼近对最小值进行修正,获得了逼近浮点和积算法的译码性能。算法的修正过程只包含简单的算术和逻辑运算,便于FPGA实现。     

一种基于高斯混合模型的导谱频率参数量化算法

提出了一种高效的基于高斯混合模型(GMM)的导谱频率(ISF)参数量化算法,算法的基本思想是利用高斯混合模型将导谱频率(ISF)参数发送给M个高斯簇,然后由高斯格型矢量量化器来量化相应高斯簇的导谱频率(ISF)参数,最终可以在M个量化值中选出频谱失真值最小的一个作为输出值。在设计高斯格型矢量量化器时,基于率失真理论提出了一种最佳比特分配算法。实验结果显示导谱频率(ISF)参数可以透明地压缩到42 bit/帧,与AMR-WB(G.722.2)的多级分裂矢量量化算法相比,节省了3 bit,减少了55%的存储空间。     

基于16位SAR模数转换器的误差校准方法

为了实现较高精度(16位及更高)的逐次逼近(SAR)ADC,提出了一种误差自动校准技术。考虑到芯片面积、功耗和精度的折中,采用了电荷再分配分段电容DAC结构,并采用准差分输入方式提高ADC的信噪比。为了消除电容失配引入的误差,提出了一种误差自动校准算法,利用误差校准DAC阵列对电容失配误差进行量化并存储在RAM中,在AD转换过程中实现误差消除。     

一种基于电流输出DAC的逐次逼近A/D转换器

设计了一种12位逐次逼近A/D转换器.该A/D转换器具有四种信号输入范围,利用电阻网络使不同量程的模拟输入与内部DAC输出范围保持一致,从而使用相同的比较器和基准实现对不同范围输入信号的A/D转换;采用一种新型分段电流源结构,利用电流信号实现内部DAC及逐次比较功能.该电路采用2 μm LC2MOS工艺实现,其积分线性误差(INL)和微分线性误差(DNL)均为±1/2 LSB,最大转换时间为12 μs.     

一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器（DDFS) . 为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland 技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩. 利用这些技术,ROM尺寸压缩了98%. 采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2. 在3.3V电源下,该芯片的功耗为167mW, 无杂散动态范围（SFDR）为61dB.     

一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器(DDFS).为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩.利用这些技术,ROM尺寸压缩了98%.采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2.在3.3V电源下,该芯片的功耗为167mW,无杂散动态范围(SFDR)为61dB.     

IEEE 802.11n LDPC译码的设计与实现

提出了一种针对IEEE 802.11n准循环非规则LDPC译码器VLSI的设计方法.设计使用了交互信息存储器最小化设计策略,交互信息存储器与基矩阵有值点一一对应原则,最大程度减少了存储器的开销.校验节点处理采用了一种层次化偏置的最小项算法来降低复杂度,并选出合适的偏置量来提高译码器性能.采用SMIC 0.13μmCMOS工艺设计并实现了该译码器,在时钟频率为133.3MHz时,最大数据吞吐率为100Mb/s,功耗为73mW.     

飞机供电系统频率瞬变检测算法研究

频率瞬变是飞机供电系统的一个重要瞬态参数,采用示波器进行抓取的方法可以得到电压值但是难以分析频率值。为实现对频率瞬变过程的快速检测与显示,基于LabVIEW采用数据拟合、时间补偿等方法设计了一种频率瞬变检测算法,在发生频率瞬变时给出文本告警并对瞬变过程进行存储和复现。利用测试电源的输出标准电压信号来验证该算法,其测试误差在允许范围内,验证了该算法的准确性。     

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.     

一种高性能低功耗直接数字频率合成器的设计

文章基于分段线性近似算法提出分段泰勒二阶近似算法，从频谱纯度分析了该算法的优越性，讨论了系数位数和分段数的选取，最后结合硬件优化的系统结构，设计实现了SFDR达102．3dB的数字频率合成器。综合结果表明，该算法实现的系统面积上要比分段线性近似算法的系统小20％，功耗上也小39．5％。与现有的其他数字频率合成器比较表明，在设计高频谱性能DDFS方面，其在功耗和面积上都具有较大优势。     

A low-power direct digital frequency synthesiser

This work presents a low power direct digital frequency synthesiser (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide lookup table ROM into two parts. The ROM size of the proposed architecture is 25% less than that of conventional lookup table DDFS. The hardware of new DDFS architecture compared to the traditional two-level table DDFS also requires less one multiplication. A synthesised 0.35 µm DDFS with an spurious free dynamic range of ?80 dB, runs up to 100 MHz and consumes 81 mW at 3.3 v. The power efficiency is 0.81 mW MHz^?1, which represents an enhancement of more than 38% compared to the conventional DDFS.     

A direct digital frequency synthesizer based on ROM free algorithm

An ROM free quadrature direct digital frequency synthesizer (DDFS) was proposed in this paper. The proposed DDFS mainly consists of two adders and two multipliers to generate quadrature outputs. The proposed DDFS was implemented in both cell-base library and ALTERA Stratix EP1S40F780C5 FPGA board for verification.     

Circuit modelling of 2-AG indirect pathway via astrocyte as a catalyst for synaptic self repair

A 32-bit read-only memory (ROM)-based direct digital frequency synthesizer with a maximum operating frequency of 2 GHz is presented. The proposed ROM-based design is capable of increasing the operation speed of traditional ROM-based DDFS by eliminating the complex control circuits and adopting a novel pseudo differential ROM. With a 14-bit partially segmented DAC based on Q² Random Walk switching scheme, the prototype DDFS produces a minimum spurious-free dynamic range of 46.38 dBc up to Nyquist frequency at the clock frequency of 2 GHz. This 0.13 μm CMOS chip occupies an active area of 0.55 mm² and dissipates 450 mW with a 1.2-V digital supply and 3.3-V analog supply.     

一种高速直接数字频率合成器及其FPGA实现

介绍了一种用于QAM调制和解调的直接数字频率合成器,该电路同时输出10位正弦和余弦两种波形,系统时钟频率为50MHz,信号的谐波小于－72dB。输出信号的范围为DC到25MHz,信号频率步长为0．0116Hz,相应的转换速度为20ns,建立时间延迟为4个时种。直接数字合成器（DDFS）采用一种有效查找表的方式生成正弦函数,为了降低ROM的大小,采用了1／8正弦波形函数压缩算法。直接数字频率合成器的数字部分由Xilinx FPGA实现,最后通过数模转换器输出。     

A 2-V, 2-GHz low-power direct digital frequency synthesizerchip-set for wireless communication

A 2 GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS LSI which synthesizes a sine wave at 55 Msps with an internal 10 b digital-to-analog converter (DAC) and Si bipolar image-reject up-converters. To achieve both high purity and low power dissipation, we developed a distortion-free up-conversion architecture and an efficient ROM output bit-width reduction technique. Operation of 2 V for the entire chip-set becomes possible because of the use of both multithreshold-voltage CMOS in the D/A converters and current-folded double-balanced mixers in the microwave up-converters. The synthesizer achieves a wide spurious-free dynamic range of 50 dB and a low power dissipation of less than 160 mW at 2 GHz     

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.     

Low-power direct digital frequency synthesis for wirelesscommunications

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-μm CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V)     

Design of low-power ROM-less direct digital frequency synthesizerusing nonlinear digital-to-analog converter

A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies