一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器(DDFS).为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩.利用这些技术,ROM尺寸压缩了98%.采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2.在3.3V电源下,该芯片的功耗为167mW,无杂散动态范围(SFDR)为61dB.     

一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器（DDFS) . 为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland 技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩. 利用这些技术,ROM尺寸压缩了98%. 采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2. 在3.3V电源下,该芯片的功耗为167mW, 无杂散动态范围（SFDR）为61dB.     

Design of low-power ROM-less direct digital frequency synthesizerusing nonlinear digital-to-analog converter

A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies     

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.     

A low-power ROM using single charge-sharing capacitor and hierarchical bit line

This paper describes a low-power read-only memory (ROM) using a single charge-sharing capacitor (SCSC) and hierarchical bit line (HBL). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a minimal voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and to make it easier to design. Furthermore, the HBL saves power by reducing the capacitance and leakage current in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with 4 K/spl times/32 bits consumes only 37% power of a conventional ROM. An SCSC-ROM chip is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 8.2 mW at 240 MHz with 2.5 V.     

基于六线逼近法的DDFS算法的实现

为了提高直接数字频率合成技术的资源利用率,结合三角函数的对称性和线性幅值逼近算法对正弦信号分段算法进行研究,提出基于六线线性逼近优化算法,使用6段不大于正弦值的均与分段的线段逼近之后,使用QE-ROM (量化-误差存储)存储线段与正弦值差值的办法,在不影响频率特征和最大误差特性基础上,实现了算法的简化,并压缩了误差补偿存储器所需存储空间。实验结果表明对于9 bit正弦输出只需使用336 bit存储器和4个加法器3个选择器一个比较器即可实现整个系统,并且最大的工作频率达到了210 MHz,共消耗110个LE,49个存储器。压缩比远远高于传统的压缩算法。     

Reduced-complexity design for triple-tunable frequency synthesiser

A new design method for a triple-tunable type DDFS-driven PLL frequency synthesiser is presented. Since only a phase accumulator is used in the DDFS (direct digital frequency synthesiser), the other parts of the DDFS such as ROM and a D/A converter can be excluded using the proposed method. Therefore, performance improvements are achieved such as circuit simplicity, reduced power consumption and switching time. In addition, the output of the designed DDFS is processed to provide a jitter-free input reference to the PLL. Simulation results show the validity and performance improvements of the proposed system, compared with the conventional system     

A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip32-b microcontroller

This paper describes the design and implementation of a fully monolithic 16-b, 1 Msample/s, low-power A/D converter (ADC). An on-chip 32-b custom microcontroller calibrates and corrects the pipeline linearity to within 0.75 LSB integral nonlinearity (INL) and 0.6 LSB differential nonlinearity (DNL). High speed and low power are achieved using a pipelined architecture. Errors resulting from capacitor mismatches, finite op-amp open loop gain, charge injection and comparator offset are removed through self-calibration. Coefficients determined during calibration are stored on chip, digitally correcting the pipeline ADC in real time during normal conversion, Full-scale errors are removed through self-calibration and an-chip multiplication. Linearity errors due to capacitor voltage coefficients are reduced using a curve fit algorithm and on-chip ROM. Digital cross-talk errors resulting from the microcontroller running at a rate of ten times the analog sampling rate have prevented implementations of fully monolithic converters of this performance class in the past. Mismatches in cross-talk due to different digital timing between calibration and correction lead to linearity errors at critical correction points. Experimental analysis and circuit techniques which overcome these problems are presented     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

This paper presents a partially switched-opamp technique for a high-speed, low-power pipelined analog-to-digital converter (ADC). Unlike a conventional switched-opamp technique, only the second stage of a two-stage opamp is switched with the enhanced power efficiency and the drawbacks of an opamp sharing technique and a conventional switched-opamp technique are addressed. The prototype of 8-bit 200-MS/s pipelined ADC is implemented in a 0.18-/spl mu/m CMOS process technology. This converter achieves 55.8-dB spurious free dynamic range, 47.3-dB signal-to-noise-plus-distortion ratio, 7.68 effective number of bits for a 90-MHz input at full sampling rate, and consumes 30-mW from a 1.8-V supply. The active area of the ADC is 0.15 mm/sup 2/.     

Low-power direct digital frequency synthesis for wirelesscommunications

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-μm CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V)     

A 15-b pipelined CMOS floating-point A/D converter

A floating-point approach can be used to extend the dynamic range of analog-to-digital (A/D) converters in applications where large signals need not be encoded with a precision greater than that required for small signals. Owing to the nonuniform nature of the quantization in a floating-point A/D converter (FADC), it is possible to sacrifice a large peak signal-to-noise ratio to obtain savings in power dissipation and area while achieving a large dynamic range. A 15-b switched-capacitor pipelined FADC has been designed with a 10-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The increased dynamic range is obtained with a three-stage pipelined variable gain amplifier, while the mantissa is determined by a uniform 10-b pipelined A/D converter. An experimental prototype of the converter has been integrated in a 0.5 μm CMOS technology. It achieves a dynamic range of 90 dB at a conversion rate of 20 MSamples/s with a total power dissipation of 380 mW     

流水线结构A/D转换器的算法改进

为了减小流水线结构A/D转换器的量化误差，提出了一种简单有效的改进算法。该算法在不附加任何额外电路的情况下，通过对模拟量化比较电平的调整，实现了舍入式流水线结构，其量化误差范围在-1／2LSB与1／2LSB之间。提出了改进算法的简化结构，并作了分析。利用MATLAB完成了算法仿真，证明该算法满足舍入式的要求，且适用于任何位数的流水线结构．     

A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.     

A 2-V, 2-GHz low-power direct digital frequency synthesizerchip-set for wireless communication

A 2 GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS LSI which synthesizes a sine wave at 55 Msps with an internal 10 b digital-to-analog converter (DAC) and Si bipolar image-reject up-converters. To achieve both high purity and low power dissipation, we developed a distortion-free up-conversion architecture and an efficient ROM output bit-width reduction technique. Operation of 2 V for the entire chip-set becomes possible because of the use of both multithreshold-voltage CMOS in the D/A converters and current-folded double-balanced mixers in the microwave up-converters. The synthesizer achieves a wide spurious-free dynamic range of 50 dB and a low power dissipation of less than 160 mW at 2 GHz     

1 V power supply, low-power consumption A/D conversion techniquewith swing-suppression noise shaping

A 1 V power supply and low-power consumption A/D conversion technique using swing-suppression noise shaping is proposed. This technique makes it possible to power the on chip A/D converter in digital LSI's directly by a one-cell battery, without a dc-dc converter. Experimental results indicated good performance for the RF-to-baseband analog interface of a digital cordless phone. The A/D converter, fabricated with a 0.5 μm CMOS process, operates on a 1 V power supply, has a 10 bit dynamic-range with a 384 ksps sampling speed and consumes only 1.56 mW     

A 12-bit 1-Msample/s capacitor error-averaging pipelined A/Dconverter

A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (×2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75-μm CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mm², including all digital logic and output buffers     

A low-power segmented nonlinear DAC-based direct digital frequency synthesizer

A 2.5-V CMOS direct digital frequency synthesizer (DDFS) with 12 bits of phase resolution and 11 bits of amplitude resolution is presented. Low power consumption is achieved using a nonlinear digital-to-analog converter (DAC). To further reduce power and area, a new technique is proposed to segment the non-linear DAC into a coarse nonlinear DAC and a number of fine nonlinear sub-DACs. The DDFS fabricated in a 0.25-/spl mu/m CMOS process occupies an active area of 1.4 mm/sup 2/. For a clock frequency of 300 MHz, it consumes 240 mW and the spurious-free dynamic range is less than 51 dB for output frequencies up to 3/8 of the clock frequency.     

DDFSGEN

This paper presents a functional compiler for the automatic design of Direct Digital Frequency Synthesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC architecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2 μm CMOS technology. A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8×2.9mm ². A maximum sample rate of 80 MHz has been attained implying a maximum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is ?46 dB.     

14位50MS/s100mW0.18μm CMOS流水线ADC

实现了一种14位40MS/s CMOS流水线A/D转换器(ADC)。在1.8V电源电压下,该ADC功耗仅为100mW。基于无采样/保持放大器前端电路和双转换MDAC技术,实现了低功耗设计,其中,无采样/保持放大器前端电路能降低约50%的功耗,双转换MDAC能降低约10%的功耗。该ADC采用0.18μm CMOS工艺制作,芯片尺寸为2.5mm×1.1mm。在40MS/s采样速率、10MHz模拟输入信号下进行测试,电源电压为1.8V,DNL在±0.8LSB以内,INL在±3.5LSB以内,SNR为73.5dB,SINAD为73.3dB,SFDR为89.5dBc,ENOB为11.9位,THD为-90.9dBc。该ADC能够有效降低SOC系统、无线通信系统及数字化雷达的功耗。