Novel Oxide Trap Behavior in Ultra Thin Gate and Its Study by PDO Method

Oxide traps for stressed MOSFET' s have been extensively investigated in the pastdecades,and the trap generation mechanism was presented[1— 4] .When oxide film isthinner than approximately 7nm,some new phenomena,such as SILC and soft...     

薄SiO2层击穿特性与临界陷阱密度

薄栅氧化层的退化、击穿与氧化层中和界面陷阱的产生相关.本文研究了在恒电流TDDB(Time-Dependent Dielectric Breakdown) 应力条件下8.9nm薄氧化层的电学特性退化、击穿情况.研究表明,电子在穿越SiO₂晶格时与晶格相互作用产生陷阱,当陷阱密度达到某一临界密度N_bd时,氧化层就击穿.N_bd可以用来表征氧化层的质量,与测试电流密度无关.击穿电量Q_bd随测试电流密度增大而减小可用陷阱产生速率的增长解释.临界陷阱密度N_bd随测试MOS电容面积增大而减小,这与统计理论相符.统计分析表明,对于所研究的薄氧化层,可看作由面积为2.56×10^-14cm²的"元胞"构成,当个别"元胞"中陷阱数目达到13个时,电子可通过陷阱直接隧穿,"元胞"内电流突然增大,产生大量焦耳热,形成欧姆通道,氧化层击穿.     

Mechanisms for hot-carrier-induced degradation inreoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing

Hot-carrier-induced degradation behavior of reoxidized-nitrided-oxide (RNO) n-MOSFETs under combined AC/DC stressing was extensively studied and compared with conventional-oxide (OX) MOSFETs. A degradation mechanism is proposed in which trapped holes in stressed gate oxide are neutralized by an ensuing hot-electron injection, leaving lots of neutral electron traps in the gate oxide, with no significant generation of interface states. The degradation behavior of threshold voltage, subthreshold gate-voltage swing, and charge-pumping current during a series of AC/DC stressing supports this proposed mechanism. RNO device degradation during AC stressing arises mainly from the charge trapping in gate oxide rather than the generation of interface states due to the hardening of the Si-SiO₂ interface by nitridation/reoxidation steps     

Characteristics degradation of the SiGe HBT under electromagnetic field stress

This paper describes a new reliability study in SiGe Heterojunction Bipolar Transistors (HBTs) by which the electromagnetic field aggression effects can be identified. Base current deviation mechanism with current gain degradation is studied for the first time. Reverse Gummel plots and capacitance characterizations indicate that the electromagnetic field stress induces traps not only at the emitter–base spacer’s oxide, but also at the collector–base spacer’s oxide. These traps induce generation/recombination centers, and leads to excess non-ideal base currents. Two-dimensional physical simulations have been used to analyse the impact of this degradation mechanism on the device behavior. As a consequence of introducing surface recombination centers at emitter–base and collector–base spacer’s oxide, a non-ideal base current rises up in agreement with the experimental data extracted. As the density of interface traps increases, the charge contributed by these interface states causes a broadening in the base current response and the capacitances deviation.     

Direct-current measurements of oxide and interface traps onoxidized silicon

A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density. The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

Relaxation effects in NMOS transistors after hot-carrier stressing

Aging studies on NMOS transistors with dry oxides at room temperature have revealed that the creation of interface traps and the trapping of positive charge in the oxide associated with hot-electron effects are not permanent, but can be reversed to some extent if the transistor drain is grounded and left for some time. The relaxation is a substantial fraction of the original degradation at low degradation values and suggests that there is an annealing of some of the traps created by stressing. This annealing follows first-order kinetics for both created interface traps and trapped oxide charge, and is characterized by relaxation times τrof 600-900 s.     

SILC-related effects in flash E2PROM's-Part I: Aquantitative model for steady-state SILC

In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO₂ gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism     

The SILC study by PDO method

Stress induced leakage current (SILC) has been discussed for a long time by many researchers. The oxide traps are believed to be the cause of SILC, but characterization of these traps is still not clear. In this paper, we demonstrate that the SILC related oxide traps can be distinguished into two kinds with different characterization parameter by PDO method. Linear fitting also shows that double oxide trap model is better than single oxide trap model.     

Consistent model for the hot-carrier degradation in n-channel andp-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V_g≈V_t) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model     

Investigation of the energy distribution of stress-induced oxide traps by numerical analysis of the TAT of HEs

This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified.     

HKMG CMOS technology qualification: The PBTI reliability challenge

We present a brief overview of Positive Bias Temperature Instability (PBTI) commonly observed in n-channel MOSFETs with SiO₂/HfO₂/TiN dual-layer gate stacks when stressed with positive gate voltage at elevated temperatures. We review the origin and present understanding of the characteristics of oxide traps that are responsible for the complex behavior of threshold voltage stability. We discuss the various physical mechanisms that are believed to govern the transient charging and discharging of these traps as the backbone of the models that have been proposed for PBTI degradation and recovery. Next we review the state-of-the-art in PBTI characterization and we present some of the key stress results on both the device as well the circuit level. Special emphasis is given on the open PBTI issues that need to be carefully addressed for a robust reliability methodology that accurately predicts PBTI lifetimes. Finally we mention some of the gate stack scaling effects on PBTI.     

Dynamic-stress-induced enhanced degradation of 1/f noise inn-MOSFETs

AC-stress-induced degradation of 1/f noise is investigated for n-MOSFETs with thermal oxide or nitrided oxide as gate dielectric, and the physical mechanisms involved are analyzed. It is found that the degradation of 1/f noise under AC stress is far more serious than that under DC stress. For an ac stress of V_G=0~0.5 V_D, generations of both interface states (ΔD_it) and neutral electron traps (ΔN_et) are responsible for the increase of 1/f noise, with the former being dominant. For another AC stress of V _G=0~V_D. a large increase of 1/f noise is observed for the thermal-oxide device, and is attributed to enhanced ΔN_et and generation of another specie of electron traps, plus a small amount of ΔD_it. Moreover, under the two types of AC stress conditions, much smaller degradation of 1/f noise is observed for the nitrided device due to considerably improved oxide/Si interface and near-interface oxide qualities associated with interfacial nitrogen incorporation     

New hot-carrier degradation mode and lifetime prediction method inquarter-micrometer PMOSFET

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs     

Degradation and breakdown of thin silicon dioxide films underdynamic electrical stress

Thin oxide MOS capacitors have been subjected to dynamic voltage stresses of different characteristics (shape, amplitude and frequency) in order to analyze the transient response and the degradation of the oxide as a function of the stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. As for the oxide degradation, the experimental data has been interpreted in terms of a phenomenological model previously developed for dc stresses. According to this model, the current evolution in voltage stresses is assumed to be related to the oxide wearout. The evolution of the current during bipolar voltage stresses shows the existence of two different regimes, the degradation being much faster at low frequencies than at high frequencies. In both regimes, the frequency dependence is not significant, and the change from one regime to the other takes place at a threshold frequency which depends on the oxide field. These trends are also observed in time-to-breakdown versus frequency data, thus suggesting a strong correlation between degradation and breakdown in dynamic stresses. The experimental results are discussed in terms of microscopic degradation models     

The impact of NMOSFET hot-carrier degradation on CMOS analogsubcircuit performance

This study presents some of the first experimental data on the impact of NMOSFET hot-carrier-induced degradation on CMOS analog subcircuit performance. Because of circuit design requirements, most NMOSFET's used for analog applications are biased in the saturation region with a low gate-to-source voltage. Under such operating conditions, in addition to interface states, significant numbers of hole traps are also generated inside the gate oxide. Because acceptor-type interface states are mostly unoccupied in the saturation region, hole traps are found to have a much more significant impact on analog NMOSFET device performance. The hot-carrier-induced degradation of analog subcircuit performance is also found to be quite sensitive to the particular circuit design and operating conditions. Circuit performance and reliability tradeoffs are examined     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

Hot-electron-induced instability in 0.5-μm p-channel MOSFETspatterned using synchrotron X-ray lithography

Radiation damage caused by X-ray includes positive oxide charge, neutral traps, and interface states. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutral traps, is not completely annealed out. The hot-electron-induced instability in p-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. However, the degradation in n-channel MOSFETs due to channel-hot carriers is not significantly increased by X-ray lithography since n-channel MOSFETs are susceptible to interface state generation by hot carriers but are relatively insensitive to the degradation due to electron trapping. The results suggest that p-channel MOSFETs in addition to n-channel MOSFETs need to be carefully examined for hot carrier-induced instability in CMOS VLSI circuits patterned using X-ray lithography and/or when the radiation damage is incurred in the back-end-of-the-line processing     

An improved HCI degradation model for a VLSI MOSFET

An improved hot carrier injection (HCI) degradation model was proposed based on interface trap gen-eration and oxide charge injection theory. It was evident that the degradation behavior of electric parameters such as I_(dlin), I_(dsat), G_m and V_t fitted well with this model. Devices were prepared with 0.35μm technology and different LDD processes, I_(dlin) and I_(dsat) after HCI stress were analyzed with the improved model. The effects of interface trap generation and oxide charge injection on device degradation were extracted, and the charge injection site could be obtained by this method. The work provides important information to device designers and process engineers.