VLSI电路中互连线的延迟及串扰的数值模拟

用数值计算方法详细地模拟了VLSI电路中金属互连线的延迟及串扰.模拟结果表明:互连线宽W同互连线节距P之比W/P=0.5~0.6是获得最小时间延迟并满足串扰限制的最佳尺寸,模拟还给出了用铜代替铝金属线及用low-k电介质(ε_low-k=0.5ε_SiO2)代替SiO₂后,延迟及串扰的改善程度.     

互连线间容性串扰对延迟的影响

集成电路的性能越来越受到互连线间寄生效应的影响,特别是耦合电容的容性串扰,容性串扰引起互连线跳变模式相关的延迟。文中从E lm ore de lay定义的角度推导了互连线受同时跳变的阶跃信号激励时开关因子的大小,分析了互连线受非同时跳变的阶跃信号激励时耦合电容对互连线延迟的影响,给出了不同激励时的受害线延迟计算方法。分析表明,开关因子为0和2不能描述耦合电容对受害线延迟影响的下上限。H sp ice模拟结果证明了分析计算的准确性。     

0.18 μm CMOS工艺下的互连线延迟和信号完整性分析

随着深亚微米工艺技术条件的应用和芯片工作频率的不断提高 ,芯片互连线越来越成为一个限制芯片性能提高和集成度提高的关键因素 :互连线延迟正逐渐超过器件延迟 ;互连线上信号传输时由于串扰引起的信号完整性问题已成为深亚微米集成电路设计所面临的一个关键问题。文中分析了芯片中器件和互连线的延迟趋势 ,模拟分析了 0 .1 8μm CMOS工艺条件下的信号完整性问题。     

工艺随机扰动下非均匀RLC互连线串扰的谱域方法分析

 考虑工艺随机扰动对互连线传输性能的影响,建立了互连线随机扰动模型,提出了一种基于谱域随机方法的互连线串扰分析新方法.该方法将具有随机扰动的耦合互连线模型在线元分析阶段进行解耦,分别采用随机伽辽金方法(SGM)和随机点匹配方法(SCM)进行串扰分析.最后,利用复逼近给出工艺随机扰动下互连线串扰噪声的解析表达式.实验结果表明本文方法不仅可以对工艺随机扰动下的非均匀耦合互连线串扰进行有效估计,相较于SPICE仿真还具有更高的计算效率.     

用于SPICE模拟高频互连效应的RLC电路模型

提出了一个用于ＳＰＩＣＥ模拟高频互连 应的ＰＣＬ互连电路模型,该模型考虑了频率对互连电感、电阻的影响,适用于从芯片间互连到芯片内互连高频效应的分析。基于所提出的互连模型,对频率达１０００ＭＨｚ时芯片内长互连线的延迟、串扰、过冲等互连寄生效应进行了分析,并指出了抑制互连效应的技术途径。     

串扰约束下超深亚微米顶层互连线性能的优化设计

优化顶层互连线性能已成为超深亚微米片上系统(SOC)设计的关键.本文提出了适用于多个工艺节点的串扰约束下顶层互连线性能的优化方法.该方法由基于分布RLC连线模型的延迟串扰解析公式所推得.通过HSPICE仿真验证,对当前主流工艺(90nm),此优化方法可令与芯片边长等长的顶层互连线(23.9mm)的延时减小到182ps,数据总线带宽达到1.43 GHz/ μ m,近邻连线峰值串扰电压控制在0.096V_dd左右.通过由本方法所确定的各工艺节点下的截面参数和性能指标,可合理预测未来超深亚微米工艺条件下顶层互连线优化设计的发展趋势.     

ULSI中的铜互连线RC延迟

随着ULSI向深亚微米特征尺寸发展，互连引线成为ULSI向更高性能发展的主要限制因素。由互连引线引起的串扰噪音及RC延迟限制了ULSI的频率性能的提高，同时考虑到电迁移和功率损耗，人们开始寻找新的互连材料；低电阻率的铜互连材料和低介电常数介质的结合可以有效地发送互连线的性能，主要讨论了互连延迟的重要性以及发送和计算延迟的方法。     

微米级平行互连线的测试结构设计

研究分析无串扰传输理想模型的条件,根据高速高密度电路板中微米级、亚毫米级互连线电磁串扰特性研究需要,首次提出微米级平行互连线的测试结构设计。经射频电路理论分析推导了测试结构对系统串扰没有影响。构建了有、无测试结构的微米级平行互连线物理模型,仿真分析后,加工制作有测试结构的微米级平行互连线电路板。研究结果表明,当数字基带信号传输频率在0~3 GHz 范围时,无测试结构仿真电路模型、有测试结构仿真电路模型、有测试结构的实验电路板,三者串扰特性吻合;微米级平行互连线的测试结构设计合理,具有工程参 考价值。     

集成电路互连线串扰的模型与分析

针对集成电路中互连线之间的串扰问题,建立了一个基于电阻和电容的串扰分析模型,给出了干扰信号为线性倾斜信号时串扰的时域响应公式,并得出了串扰峰值的估算公式,明确了干扰信号上升沿对串扰的影响。利用该公式,能对全局互连性能的影响做出正确的估计,在互连布局前预先进行路由规划和资源选择。     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

Closed-form expressions for interconnection delay, coupling, andcrosstalk in VLSIs

A closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived. Expressions are also derived for the voltage slope and transition time of the RC interconnection and for coupling capacitance and crosstalk voltage height, which can be used in VLSI designs. Using the expressions, the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed     

Modeling of interconnect capacitance, delay, and crosstalk in VLSI

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations     

Design of Optical Rearrangeable Nonblocking MINs Under Various Crosstalk Constraints

Optical interconnection networks suffer from the intrinsic crosstalk problem that should be overcome to make them work properly. Vertical stacking of optical banyan networks is a novel scheme for constructing nonblocking optical multistage interconnection networks (MINs). Rearrangeable nonblocking optical MINs are feasible since they have lower complexity than their strictly nonblocking counterparts. In this paper, we determine the sufficient condition for these MINs to be rearrangeable nonblocking under various crosstalk constraints. We show how the crosstalk constraint affects the design of rearrangeable nonblocking MINs and demonstrate that these networks can tolerate a stricter crosstalk constraint without increasing their hardware complexity significantly. The results in the paper will be useful in designing optical MINs with reasonable hardware cost and crosstalk level.     

非平行微带线间的串扰抵消研究

非平行微带线是印刷电路板(PCB)上不可避免的互连结构。针对PCB 上非平行微带线间的串扰问题,用平行微带线近似非平行微带线,把平行耦合微带线间的串扰抵消方法应用到非平行耦合微带线中,提出了利用耦合传输线信道传输矩阵方法来进行远端串扰抵消,在对非平行耦合传输线信道传输矩阵进行特征值分解的基础上构建串扰抵消电路。仿真了非平行微带线间夹角分别为q=3°、5°、10°时的串扰,结果表明,该方法可以有效改善非平行微带线上信号眼图的质量,串扰抵消效果良好。     

VLSI interconnect issues in definitive and stochastic environments

A system designer needs to estimate the behavior of a system interconnection based on different patterns of switching which happen around an interconnect. Two different scenarios are supposed to estimate the effect of interconnect issues on system performance. First, based on a normalization technique for decreasing the number of a transfer function variables, a definitive environment for one interconnect is considered and an optimized look-up-table for the wire time delay is generated. Using some sampling methods, fast accessible look-up-tables are proposed for CAD tools in very simple and small one. A 4×4×4 table for the wire delay is introduced which results in very fast estimation. The average and maximum error of this look-up-table is less than 1% and 7.7% respectively, compared to HSPICE results. Second, the statistical environment of a wire in a BUS configuration is studied for all possible different switching patterns happening for the wires. Estimating the BUS main problems, including power consumption, crosstalk, and propagation delay for a random environment, which a wire senses in wide BUS, is only possible with statistical parameters like mean and variance. All simulations are done considering both wire inductive and capacitive couplings in HSPICE. Also, the secondary effect of crosstalk on propagation delay and power consumption is considered. The simulation results show 3.81% of BUS input switching can lead to a wrong decision on its wire load due to the crosstalk induced voltages in 90 nm technology. The average induced crosstalk aware power consumption is 94 μW. Also, the average of maximum crosstalk on the load can be as high as 25% of the V_dd.     

A 3D multilayer optical network on chip based on mesh topology

Optical Network-on-Chip (ONoC) is becoming a promising solution for high performance on chip interconnection, which draws much attention from many researchers. ONoC combined with 3D integration technology can address some issues of two-dimensional ONoC such as long distance and limited scalability, which have been shown to be effective solutions for further promoting the performance of ONoC. However, the infeasibility of most existing routers with four or five ports poses a problem in 3D optical interconnect as seven-port optical routers are required in 3D networks. To solve this problem, in this paper, we propose a 3D multilayer optical network on chip (3D MONoC) based on Votex, a non-blocking optical router with seven ports. We describe the optical router and the 3D network in detail. The proposed router architecture not only realizes 3D interconnection and can be utilized in most 3D ONoC, but also can be beneficial in achieving smaller area, lower cost of ONoC. We compare Votex with the traditional \(7\times 7\) optical router based on crossbar, which indicated that Votex can save cost. Moreover, we make a comparison of 3D MONoC employing Votex against its 2D counterpart. Simulation results show that the performance including ETE delay and throughput of 3D MONoC can be improved.     

用修正特征法模型求解高速VLSI中有耗互连线的瞬态响应

本文提出了用于高速集成电路系统中有耗互连线瞬态响应求解的一个计算模型及其相应的算法。传统的特征法在用于求解无耗传输线或满足ＬＧ＝ＲＣ的有耗传输线时具有简单的递归形式和较高的计算效率,但不能用于一般的有耗传输线。本文在特征法的基础上,通过适当的参数修正,建立了一般有耗传输线瞬态响应的近似特征模型,导出了其对时间变量递归形式的计算公式。     

An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

Microwave frequency crosstalk model of redistribution line patterns on wafer level package

As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer S-parameter measurements and was fitted to the measurements made at up to 5 GHz.