大规模集成电路互连线的串扰估计

建立了一个基于电阻和电容的串扰分析模型,给出了干扰信号为线性倾斜信号时串扰的时域响应公式,得出了串扰峰值的估计公式,明确了干扰信号上升沿、互连线的电阻和耦合电容等对串扰的影响,并且利用Hyperlynx软件包进行仿真,仿真结果证明了理论分析的正确性.     

IC中多余物缺陷对信号串扰的定量研究

该文研究了铜互连线中的多余物缺陷对两根相邻的互连线间信号的串扰,提出了互连线之间的多余物缺陷和互连线之间的互容、互感模型,用于定量的计算缺陷对串扰的影响。提出了把缺陷部分单独看作一段RLC电路模型,通过提出的模型研究了不同互连线参数条件下的信号串扰,主要研究了铜互连线的远端串扰和近端串扰,论文最后提出了一些改进串扰的建议。实验结果证明该文提出的信号串扰模型可用于实际的电路设计中,能够对设计人员设计满足串扰要求的电路提供指导。     

柔性可延展电路中互连结构设计及布局优化

针对柔性可延展电路由于不合理的互连结构设计和布局而造成的串扰问题,提出一种基于响应面法对柔性可延展电路互连结构进行设计与布局的方法。以柔性可延展电路中的通用互连结构为研究对象,通过正交实验和方差分析,筛选出对串扰存在显著性影响的因素。基于正交设计分析结果,运用中心复合实验设计法获得样本数据,利用ANSYS Electronic Desktop获得串扰响应值,构建串扰与影响因子之间的二阶多项式响应面模型,以近端串扰和远端串扰之和的最小值为优化目标建立优化模型,通过优化算例验证了该方法的可行性,为可延展通用互连导线的优化与布局提供了参考依据。     

两相邻耦合RC互连的串扰效应及其抑制

随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。     

高密度封装中互连结构差分串扰建模与分析

针对传统模型存在较大分析误差的问题,提出高密度封装中互连结构差分串扰建模与分析。在对互连结构差分传输线耦合关系分析的基础上,建立了四线差分结构串扰模型。运用该模型对互连结构差分串扰中的电阻、电容以及电感进行等效分析,解决高密度封装中互连结构差分串扰问题。经试验证明,此次建立模型平均误差为0.042,满足抑制高密度封装中互连结构差分串扰问题的精度需求。     

两相邻耦合RLC互连的串扰估计

本文建立了一种考虑电感耦合效应的两相邻耦合互连模型,基于传输函数直接截断的方法给出了其互连串扰的解析表达式.讨论了该解析公式在局部互连和全局互连两种情况下的应用,其结果相对于HSPICE的误差小于10%.它可以用于考虑串扰效应的版图优化.     

工艺随机扰动下非均匀RLC互连线串扰的谱域方法分析

 考虑工艺随机扰动对互连线传输性能的影响,建立了互连线随机扰动模型,提出了一种基于谱域随机方法的互连线串扰分析新方法.该方法将具有随机扰动的耦合互连线模型在线元分析阶段进行解耦,分别采用随机伽辽金方法(SGM)和随机点匹配方法(SCM)进行串扰分析.最后,利用复逼近给出工艺随机扰动下互连线串扰噪声的解析表达式.实验结果表明本文方法不仅可以对工艺随机扰动下的非均匀耦合互连线串扰进行有效估计,相较于SPICE仿真还具有更高的计算效率.     

柔性可延展耦合电路互连结构频域与时域特性分析

串扰作为信号完整性的重要影响因素之一,在进行高速可延展电路设计时,需要对电路中互连结构之间的串扰进行分析,以验证结构的合理性。以耦合可延展通用互连结构为研究对象,在高速电路中运用有限元法对形变后的耦合可延展通用互连结构进行频域分析,研究了频率以及形变对电路中相邻导线间串扰产生的影响。利用频域分析得到的S参数建立时域分析的电路模型,对耦合可延展通用互连结构进行了时域分析,研究频率以及形变对导线端口输出电压产生的影响,对频域分析结果进行验证,为可延展柔性电路互连结构的设计提供了参考。     

考虑工艺波动的互连串扰的峰值统计模型

随着集成电路特征尺寸的不断减小,互连线的串扰噪声对工艺波动的灵敏度也在相应增加。通过分析互连几何参数波动对互连寄生参数的影响,得到其近似的函数关系表达式,在此基础上建立了考虑工艺波动的串扰噪声的统计模型。利用该模型可以得到互连串扰噪声均值和标准差的解析表达式。计算结果表明：和HSPICE相比,该方法在确保计算精度的前提下大大缩短了计算时间,在超大规模集成电路互连信号完整性的分析和优化中具有一定的应用前景。     

若干因素下的高速互连线间的串扰规律研究

信号完整性中的串扰问题是目前高速电路设计中的难点和重点问题。利用高速电路仿真软件HSPICE和MATLAB软件对高速电路中的互连线串扰模型进行了仿真分析,总结了三种变化因素下互连线间的串扰规律,对部分串扰规律进行了探索性的研究。     

一种新的集成电路互连线串扰模型和估计公式

建立了一个考虑分布电阻,分布电容的互连线混П模型,在这个模型的基础上,分析了终端在最坏条件下的串扰响应,并推导了三阶S域系数的精确表达式,最终,获得了一个新的互连线串扰响应的估计公式,通过与SPICE模拟的结果相比较,该文的模拟结果非常接近实际电路的串扰响应,与相关文献所发表的结果相比较,该模型更符合实际情况,结果也更精确。     

Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns

This paper presents an in-depth analysis of signal slew and skew variations in coupled inductive lines for different switching patterns. It is revealed that variations of rise/fall time and skew alter the behavior of coupled inductive lines under different switching patterns. We observe that crosstalk noise reduces with increasing signal skew, and the impact of skew variation on crosstalk noise is more prominent for lines with strong capacitive coupling. A performance comparison is done between power supply and ground line as inductive shield, and it is found that ground lines work better than power lines in inductive crosstalk minimization. The 100%-delay measurement technique has been proposed as opposed to the conventional 50%-delay method, and we notice that the 50%-delay technique underestimates the propagation delay for an inductive dominant line with varying signal slew times. Closed-form equations for propagation delay in terms of signal slew time have been derived, which are within 9% of HSPICE-simulated results for a set of interconnect structures. These expressions are simple, and accuracy increases with growing number of interconnect lines.      

深亚微米SoC芯片物理设计中基于串扰的时序收敛方法

当芯片设计进入深亚微米，串扰效应引起大量的设计违规，尤其是对时序收敛产生很大的影响。实际上串扰对电路时序性能的影响非常难估计，它不仅取决于电路互联拓扑，而且还取决于连线上信号的动态特征。文章从串扰延时的产生原因开始分析，并提出了在O．18μm及以下工艺条件下对串扰延时进行预防．分析和修复的时序收敛方法。     

Crosstalk fault modeling in defective pair of interconnects

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the deep sub-micron (DSM) chips. In this paper, we describe the line-defect-based crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model is very fast (at least 11 times faster than PSPICE model) and its accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs marginally.     

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.     

Performance Analysis of Microstriplines Interconnect Structure with Novel Guard Trace as Parallel Links for High Speed Dram Interfaces

Wireless communication have progressed so fast in recent years with the increased frequency of operation, faster signal speed, reduced feature size and increased the integration of analog and digital blocks within a constrained space. These made the signal integrity analysis is a challengine task to printed circuit board designers. The signal integrity effects need to be mitigated by the proper design of high speed interconnects. In order to reduce crosstalk and crosstalk induced jitter in high speed parallel links to DRAM interface, a novel parallel microstriplines with U shaped guard trace interconnect structure is proposed. The crosstalk performance of the proposed interconnect structure, it can be implemented in DRAM board and compared with the conventional guard intervening scheme. The proposed structure increased the maximum data rate from 800 Mbps to 3.3 Gbps and reduced CIJ more than 2 ps.

     

Noise-aware interconnect power optimization in domino logic synthesis

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized, which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption about 14% on average.     

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.