GaAs metal insulator field effect transistors with excellentintrinsic transconductance and stable drain currents using (NH4)2Sx chemical treatment

Metal insulator semiconductor field effect transistors (MISFETs) and MIS capacitors are fabricated using Al metal-gate and PECVD silicon nitride (Si₃N₄) gate-insulator on commercial GaAs epitaxial wafers after treating the channel regions with (NH₄)₂S_x. It is shown that the post metallization annealing (PMA) of these devices improves the transconductance and reduces the interface state density (D_it) considerably. This is attributed to the additional passivation effect of hydrogen diffusing to the interface from the Si ₃N₄ during the PMA. An intrinsic transconductance of 30.7 mS/mm which is 75% of the theoretical maximum limit of 40.5 mS/mm has been achieved using silicon nitride gate insulator thickness of 1100 Å. Stability of the drain currents in these devices is demonstrated to be excellent     

Stable gallium arsenide MIS capacitors and MIS field effecttransistors by (NH4)2Sx treatment andhydrogenation using plasma deposited silicon nitride gate insulator

The beneficial effects of sulfur passivation of gallium arsenide (GaAs) surface by (NH₄)₂S_x chemical treatment and by hydrogenation of the insulator-GaAs interface using the plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride gate dielectric film as the source of hydrogen are illustrated by fabricating Al/PECVD silicon nitride/n-GaAs MIS capacitors and metal insulator semiconductor field effect transistors (MISFET). Post metallization annealing (PMA) at temperatures in the range 450-550°C is shown to be the key process for achieving midgap interface state density below 10 ¹¹/cm²/eV and maximum incremental transconductance, which is about 75% of the theoretical maximum limit. MIS capacitors are fabricated on (NH₄)₂S_x treated GaAs substrate using gate dielectrics such as PECVD SiO ₂ and silicon oxynitride to demonstrate that the PMA is less effective with these dielectrics because of their lower hydrogen content. The small signal AC transconductance, g_ms measurements on MISFETs fabricated using silicon nitride, have shown that the low-frequency degradation of g_ms is almost absent in the devices fabricated on (NH₄)₂S_x-treated GaAs substrates and subjected to PMA. The drain current stability in these devices is demonstrated to be excellent, with an initial drift of only 2% of the starting value. The dual role of silicon nitride layer, namely, protection against loss of sulfur and an excellent source of hydrogen for additional surface passivation along with sulfur is demonstrated by comparing the transconductance of MISFETs fabricated on GaAs substrates annealed without the nitride cap after the (NH₄)₂S _x treatment     

Unpinned GaAs MOS capacitors and transistors

Metal-oxide-semiconductor (MOS) capacitors and field-effect transistors (MOSFETs) in the GaAs semiconductor system using an unpinned interface are described. The structures utilize plasma-enhanced chemical-vapor deposition (PECVD) for the silicon-dioxide insulator on GaAs that has been terminated with a few monolayers of silicon during growth by molecular beam epitaxy. Interface densities in the structures have been reduced to ~10¹² cm^-2·eV^-1 . High-frequency characteristics indicate strong inversion of both p-type and n-type GaAs. The excellent insulating quality of the oxide has allowed demonstration of quasi-static characteristics. MOSFETs operating in depletion mode with a transconductance of 60 mS/mm at 8.0-μm gate lengths have been fabricated     

Charge Storage in Pentacene/Polymethylmethacrylate Memory Devices

The electrical behavior of organic metal–insulator–semiconductor (MIS) structures incorporating a layer of self-assembled metallic nanoparticles is described. These have been based on thermally evaporated pentacene (semiconductor) and spin-coated polymethylmethacrylate (insulator). The MIS devices containing the nanoparticles exhibited significant hysteresis in their capacitance-versus-voltage and conductance-versus-voltage characteristics, which was attributed to the charging and discharging of the nanoparticles. The memory structure reported here offers a useful advance in the development of flexible organic memory structures.      

Demonstration of GaN MIS diodes by using AlN and Ga2O3(Gd2O3) as dielectrics

GaN MIS diodes were demonstrated utilizing AlN and Ga₂O₃(Gd₂O₃) as insulators. A 345 Å of AlN was grown on the MOCVD grown n-GaN in a MOMBE system using trimethylamine alane as Al precursor and nitrogen generated from a SVT RF N₂ plasma. For the Ga₂O₃(Gd₂O₃) growth, a multi-MBE chamber was used and a 195 Å oxide was E-beam evaporated from a single crystal source of Ga₅Gd₃O₁₂. The forward breakdown voltage of AlN and Ga₂O₃(Gd₂O₃) diodes are 5 and 6 V, respectively, which are significantly improved over 1.2 V from that of a Schottky contact. From the C–V measurements, both kinds of diodes showed good charge modulation from accumulation to depletion at different frequencies. The insulator/GaN interface roughness and the thickness of the insulator were measured with X-ray reflectivity.     

Electrical characteristics of gold nanoparticle-embedded MIS capacitors with parylene gate dielectric

Memory characteristics of gold nanoparticle-embedded metal–insulator–semiconductor (MIS) capacitors with polymer (parylene-C) gate insulating material are investigated in this study. The gold nanoparticles used in this work were synthesized by the colloidal method. Current density versus voltage curves obtained from the MIS capacitors exhibit better performance for the parylene-C gate insulator, compared with other gate insulating materials. Capacitance versus voltage (C–V) curves show a flat band voltage shift, which indicates the possibility of charge storage in the gold nanoparticles. In addition, the charge retention characteristic for the gold nanoparticle-embedded MIS capacitor is described in this paper.     

Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

Evaluation of the valence band discontinuity ofSi/Si1-xGex/Si heterostructures by application ofadmittance spectroscopy to MOS capacitors

In this study, admittance spectroscopy is applied for the first time to MOS capacitors fabricated on Si/Si_1-xGe_x/Si double-heterostructures, in order to evaluate the valence band discontinuity ΔE_v at the Si/Si_1-xGe_x interface. The principle of the measurement is presented and verified by the experimental results. A new feature of admittance spectroscopy applied to MOS capacitors is the ability to select the interface whose barrier is measured, by controlling the gate voltage. This fact is confirmed by the measurement of MOS capacitors, which include a SiGe well with different Ge contents at the front and the back interfaces. It is found from this measurement that, while ΔE_v at the back interface of the double-heterostructure is measured under slight depletion conditions for MOS capacitors, ΔE_v averaged between the front and the back interfaces is measured under accumulation conditions. The Ge_x content dependence of the measured ΔE_v is found to be in fairly good agreement with the theoretical values     

Properties of Si/sub 3/N/sub 4//Si/sub x/Ge/sub 1-x/ metal-insulator-semiconductor capacitors

The density of fast interface states was studied in Si/sub 3/N/sub 4//Si/sub 0.8/Ge/sub 0.2/ metal-insulator-semiconductor (MIS) capacitors. The interface state density does not appear to be strongly affected by the presence of a thin Si interlayer between the nitride and SiGe alloy. This is in contrast to the results when SiO/sub 2/ is used as the insulator material in similar structures.<>     

Interfaces analysis by impedance spectroscopy and transient current spectroscopy on semiconducting polymers based metal–insulator–semiconductor capacitors

Impedance and transient current measurements on metal–insulator–semiconductor (MIS) capacitors are used as tools to thoroughly investigate the bulk and interface electronic transport properties of semiconducting polymers, i.e. poly(3-hexylthiophene) (P3HT). Distinct features were observed at both interfaces, i.e. metal–semiconductor and semiconductor–insulator. The results revealed a dispersive transport in the bulk due to the band tail of the localized states, presence of interface states at the interface between the insulator and the semiconductor and formation of a less conductive small layer at the interface semiconductor–metal contact due to intrusions of sputtered Au particles. Effects of self-assembled monolayers (SAMs) treatments of the gate insulating dielectric were investigated showing that treating the gate dielectric with either ozone or hexamethyldisilazane (HMDS) or octyltrichlorosilane (OTS) alter not only the interface semiconductor–insulator but the bulk properties as well. An exponential density of states with a width parameter of 38–58 meV depending on the surface treatment was found to be representative of the band tail of P3HT. Though both OTS and HMDS treatments slightly increase the density of interface states, only OTS treated samples showed a decrease in disorder parameter of the bulk. The latter fact can be attributed to an increase of the grain size due to a favored π-π stacking film growth. An outcome explaining the already reported increase of the lateral mobility and decrease of the vertical mobility observed upon OTS treatment of the gate insulating dielectric in poly(3-hexylthiophene) based devices.     

New technique for measuring the threshold voltage in MOS devices

The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state/steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) f_m, are read. Several gate voltage versus optimum frequencies (f_m–V_G) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The (f_m–V_G) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional I_D–V_GS and simulation methods as well as that supplied by the device manufacturer.     

Electroluminescence from MIS silicon-based light emitters with arrays of self-assembled Ge(Si) nanoislands

We report on the electroluminescence from silicon-based metal–insulator–semiconductor (MIS) diodes with arrays of self-assembled Ge(Si) nanoislands. Aluminum oxide (Al₂O₃) is used as an insulator material in the MIS contact. Variations in the electroluminescence spectra caused by changing the metal work function are examined. The intense electroluminescence from Ge(Si) nanoislands localized at a distance of 50 nm from the insulator–semiconductor interface is observed at room temperature. The emission spectrum is found to be controlled by choosing the design of the semiconductor structure and the barrier height for injected carriers.     

SiC MOSFETs with thermally oxidized Ta2Si stacked on SiO2 as high-k gate insulator

In this paper, we compare the electrical characteristics of MOS capacitors and lateral MOSFETs with oxidized Ta₂Si (O-Ta₂Si) as a high-k dielectric on silicon carbide or stacked on thermally grown SiO₂ on SiC. MOS capacitors are used to determine the dielectric and interfacial properties of these insulators. We demonstrate that stacked SiO₂/O-Ta₂Si is an attractive solution for passivation of innovative SiC devices. Ta₂Si deposition and oxidation is totally compatible with standard SiC MOSFET fabrication materials and processing. We demonstrate correct transistor operation for stacked O-Ta₂Si on thin thermally grown SiO₂ oxides. However the channel mobility of such high-k MOSFETs must be improved investigating the interface properties further.     

Compositional dependence of permittivity in quarternary III–V semiconductor compounds

An empirical relation for the relative permittivity in quarternary III–V semiconductor compounds is suggested as a function of composition. The expression for the permittivity of ternary III–V compounds can be obtained from that as a special case which is identical to that already available in the literature. Graphs have been plotted for static and optical permittivities against composition for the widely used quarternary semiconductor In_1-xGa_xAs_yP_1-y and are discussed.     

Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1E11 eV^-1cm^-2), gate leakage property (3.6E3 A/cm^2 at Vg = 1 V + Vfb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.     

Effect of annealing on GaN-insulator interfaces characterized by metal-insulator-semiconductor capacitors

GaN metal-oxide-semiconductor (MOS) capacitors have been used to characterize the effect of annealing temperature and ambient on GaN-insulator interface properties. Silicon dioxide was deposited on n-type GaN at 900 /spl deg/C by low-pressure chemical vapor deposition and MOS capacitors were fabricated. The MOS capacitors were used to characterize the GaN-SiO/sub 2/ interface with a low interface-state density of 3 /spl times/ 10/sup 11/ cm/sup -2/eV/sup -1/ at 0.25 eV below the conduction band edge, even after annealing in N/sub 2/ at temperatures up to 1100 /spl deg/C; however, insulator properties were degraded by annealing in NO and NH/sub 3/ at 1100 /spl deg/C.     

Electrical properties of metal–HfO2–silicon system measured from metal–insulator–semiconductor capacitors and metal–insulator–semiconductor field–effect transistors using HfO2 gate dielectric

Metal–insulator–semiconductor (MIS) capacitors and metal–insulator–semiconductor field effect transistors (MISFETs) incorporating HfO₂ gate dielectrics were fabricated using RF magnetron sputtering. In this work, the essential structures and electrical properties of HfO₂ thin film were examined. The leakage current measured from MIS capacitors depends on the sputtering gas mixture and the annealing temperature. The best condition to achieve the lowest leakage current is to perform the annealing at 500 °C with a mixture of 50% N₂ and 50% O₂ gas ratio. Aluminum is used as the top electrode. The Al/HfO₂ and the HfO₂/Si barrier heights extracted from Schottky emission are 1.02 eV and 0.94 eV, respectively. An Al/HfO₂/Si energy band diagram is proposed based on these results.     

Au/SnO2/n-Si (MOS) structures response to radiation and frequency

Metal-insulator-semiconductor (MOS) structures with insulator layer thickness of 290 Å were irradiated using a ⁶⁰Co (γ-ray) source and relationships of electrical properties of irradiated MOS structures to process-induced surface defects have been investigated both before and after γ-irradiation. The density of surface state distribution profiles of the sample Au/SnO₂/n-Si (MOS) structures obtained from high-low frequency capacitance technique in depletion and weak inversion both before and after irradiation. The measurement capacitance and conductance are corrected for series resistance. Series resistance (Rs) of MOS structures were found both as function of voltage, frequency and radiation dose. The C(f)-V and G(f)-V curves have been found to be strongly influenced by the presence of a dominant radiation-induced defects. Results indicate interface-trap formation at high dose rates (irradiations) is reduced due to positive charge build-up in the semiconductor/insulator interfacial region (due to the trapping of holes) that reduces the flow rate of subsequent holes and protons from the bulk of the insulator to the Si/SnO₂ interface. The series resistance decreases with increasing dose rate and frequency the radiation-induced flat-band voltage shift in 1 V. Results indicate the radiation-induced threshold voltage shift (ΔV_T) strongly dependence on radiation dose rate and frequency.     

Effects of minute impurities (H, OH, F) on SiO2/Siinterface as investigated by nuclear resonant reaction and electron spinresonance

The effects of minute amounts of impurities (H, OH, and F) in SiO ₂ are investigated to obtain a guideline for improving the reliability of MOS devices. To examine the behavior of hydrogen, deuterium (D) is adopted as a tracer. The quantity of deuterium dissolved in SiO₂ is measured by the D(³He,p)⁴He nuclear resonant reaction (NRR) technique. The Influence of the impurities on the SiO₂-Si interface structure is studied by electron spin resonance (ESR) measurement. Hot-carrier injection with MOS capacitors and transistors are examined to determine the effects of minute impurities on the electrical characteristics of gate SiO₂ and the correlation of this effect with the NRR and ESR experimental results. It was found that significant amounts of D₂O are diffused into SiO₂ , even at 200°C, and these dissolved D₂O molecules are eliminated at temperatures above 700°C. The number of unpaired bonds at the interface increases with decrease of dissolved water in SiO ₂. The disappearance of the interface traps after high-temperature annealing above 800°C is thought to be due to the viscous flow of SiO₂ and to the interface reoxidation. Reducing the hydrogen and relaxing the interface strain are essential for improving the MOS device endurance against hot carriers     

Influence of ionizing radiation in electronic and optoelectronic properties of III–V semiconductor compounds

The interaction between radiation and matter is very important in the study of materials used in the aerospace industry. The improvement of the resistance of various devices is crucial. In the present work we have produced simulation results of damages induced in electronic devices of III–V semiconductor compounds, using SRIM-TRIM, CASINO and GEANT4 programs. The energies used for ⁺ particles, SRIM-TRIM, were from 500 keV to 4 MeV for both FETs and HEMTs and the energies used for β⁻ particles, CASINO, were from 1 to 500 keV.