Memory effects in hybrid silicon-metallic nanoparticle-organic thin film structures

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on silicon substrates and using organic thin films as the dielectric layers. These insulating thin films were produced by different methods, including spin-coating (polymethylmethacrylate), thermal evaporation (pentacene) and Langmuir–Blodgett deposition (cadmium arachidate). Gold nanoparticles, deposited at room temperature by chemical self-assembly, were used as charge storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A maximum memory window of 2.5 V was achieved by scanning the applied voltage of an Al/pentacene/Au nanoparticle/SiO₂/p-Si structure between 9 and −9 V.     

Metal–Insulator–Semiconductor Coaxial Microfibers Based on Self‐Organization of Organic Semiconductor:Polymer Blend for Weavable,Fibriform Organic Field‐Effect Transistors

With the increasing importance of electronic textiles as an ideal platform for wearable electronic devices, requirements for the development of functional electronic fibers with multilayered structures are increasing. In this paper, metal–polymer insulator–organic semiconductor (MIS) coaxial microfibers using the self‐organization of organic semiconductor:insulating polymer blends for weavable, fibriform organic field‐effect transistors (FETs) are demonstrated. A holistic process for MIS coaxial microfiber fabrication, including surface modification of gold microfiber thin‐film coating on the microfiber using a die‐coating system, and the self‐organization of organic semiconductor–insulator polymer blend is presented. Vertical phase‐separation of the organic semiconductor:insulating polymer blend film wrapping the metal microfibers provides a coaxial bilayer structure of gate dielectric (inside) and organic semiconductor (outside) with intimate interfacial contact. It is determined that the fibriform FETs based on MIS coaxial microfiber exhibit good charge carrier mobilities that approach the values of typical devices with planar substrate. It additionally exhibits electrical property uniformity over the entire fiber surface and improved bending durability. Fibriform organic FET embedded in a textile is demonstrated by weaving MIS coaxial microfibers with cotton and conducting threads, which verifies the feasibility of MIS coaxial microfiber for use in electronic textile applications.     

Nickel nanoparticle deposition at room temperature for memory applications

In this work we investigate the non-volatile memory behavior of Ni nanoparticles embedded within an insulating matrix. Nickel nanoparticles are deposited at room temperature by a new high-vacuum technique over a 4 nm tunneling thermal SiO₂ layer followed by the deposition of HfO₂ as a control insulator. Memory windows of ∼1.5V are observed in MOS capacitors at gate pulse voltages of 8V. Charge retention for write and erase state clearly indicate long time charge storage behavior.     

Fixed negative interface charges compromise organic ferroelectric field-effect transistors

Capacitance–voltage (C–V) and current–voltage measurements have been undertaken on metal-ferroelectric-semiconductor capacitors and ferroelectric field-effect transistors (FeFETs) using the ferroelectric polymer poly(vinylidenefluoride-trifluoroethylene) as the gate insulator and poly(3-hexylthiophene) as the active semiconductor. C–V measurements, voltage-dependence of gate currents and FeFET transfer characteristics all confirm that ferroelectric polarization is stable and only reverses when positive/negative coercive fields are exceeded for the first time. The apparent instability observed following the application of depletion voltages arises from the development of a negative interfacial charge which more than compensates the ferroelectric-induced shift, resulting in a permanent shift in threshold voltage to positive values. Application of successive bipolar voltage sweeps to a diode-connected FeFET show that significant remanent polarization is only induced in an unpoled device when the coercive field is exceeded during the first application of accumulation voltages. This initial polarization and its growth during subsequent bipolar voltage sweeps is accompanied by the accumulation of the fixed interfacial negative charges which cause the positive turn on voltages seen in C–V and transfer characteristics. The origin of the negative charge is ascribed either to layers of irreversible ferroelectric domains at the insulator surface or to the drift to the insulator-semiconductor interface of F^- ions produced electrolytically during the application of accumulation voltages.     

Interfaces analysis by impedance spectroscopy and transient current spectroscopy on semiconducting polymers based metal–insulator–semiconductor capacitors

Impedance and transient current measurements on metal–insulator–semiconductor (MIS) capacitors are used as tools to thoroughly investigate the bulk and interface electronic transport properties of semiconducting polymers, i.e. poly(3-hexylthiophene) (P3HT). Distinct features were observed at both interfaces, i.e. metal–semiconductor and semiconductor–insulator. The results revealed a dispersive transport in the bulk due to the band tail of the localized states, presence of interface states at the interface between the insulator and the semiconductor and formation of a less conductive small layer at the interface semiconductor–metal contact due to intrusions of sputtered Au particles. Effects of self-assembled monolayers (SAMs) treatments of the gate insulating dielectric were investigated showing that treating the gate dielectric with either ozone or hexamethyldisilazane (HMDS) or octyltrichlorosilane (OTS) alter not only the interface semiconductor–insulator but the bulk properties as well. An exponential density of states with a width parameter of 38–58 meV depending on the surface treatment was found to be representative of the band tail of P3HT. Though both OTS and HMDS treatments slightly increase the density of interface states, only OTS treated samples showed a decrease in disorder parameter of the bulk. The latter fact can be attributed to an increase of the grain size due to a favored π-π stacking film growth. An outcome explaining the already reported increase of the lateral mobility and decrease of the vertical mobility observed upon OTS treatment of the gate insulating dielectric in poly(3-hexylthiophene) based devices.     

Capacitance-voltage characterization of pulsed plasma polymerized allylamine dielectrics for flexible polymeric field effect transistors

Polyallylamine films, deposited on Si wafers by radio frequency (RF) pulsed plasma polymerization (PPP), were employed as insulating layers of metalinsulator-semiconductor (MIS) capacitors. The insulating polymer films were deposited at plasma reactor temperatures of 25°C and 100°C. Multiple frequency capacitance-voltage (C-V) measurements indicated that an in-situ heat treatment during film deposition increased the insulator dielectric constant. The dielectric constant, calculated from the C-V data, rose from 3.03 for samples with no heat treatment to 3.55 for samples with an in-situ heat treatment. For both sample sets, the I-V data demonstrates a low leakage current value (<20 fA) up to 100 V. Capacitance-time (C-t) measurements were also used to characterize the mobile ions in the polymer that migrate over time with applied voltage. Results indicate that the polymer layers contain few electrically active defect centers and virtually no pinholes. Hysteresis in the C-V curves with differing sweep directions was more pronounced for in-situ heat-treated samples indicative of mobile charge.     

Analytical investigation of surface potential and related properties of metal/insulator/III–V semiconductor capacitors

An analytical study of the effect of an applied gate bias on the potential and electron density in the semiconductor of metal/insulator/III–V semiconductor (III–V MIS) capacitors is carried out. For this, Poisson's equation is rewritten to a form amenable to analytical study. Si₃N₄ is used as an insulator layer for the MIS capacitors. In order to highlight the advantages of III–V MIS capacitors over metal-SiO₂---Si (MOS) capacitors, the ideal case free from interface traps is considered and theoretical results are obtained also for MOS capacitors. The calculated results strongly demonstrate the superiority of InGaAs MIS and GaAs MIS capacitors to Si MOS capacitors and pinpoint the situation in which the interface states are present.     

Unified tunnelling-diffusion theory for Schottky and very thin MOS structures

We derive general formulae for calculating the transport of free charge carriers in a MOS structure with a thin insulating layer. In particular, we obtain relationships for boundary concentrations of free charge carriers on the insulator–semiconductor interface and for the current densities flowing through the MOS structure. Our direct tunnelling-diffusion approach makes the well known thermionic emission–diffusion theory for the Schottky interface applicable also to metal–insulator–semiconductor barriers with a very thin insulator layer. We demonstrate how direct tunnelling through the insulating layer and drift–diffusion of free charge carriers in the semiconductor affect the I–V and C–V curves and the boundary concentrations needed to numerically solve the continuity equations.     

Trapping and reliability issues in GaN-based MIS HEMTs with partially recessed gate

This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al₂O₃. Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator.The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Microcapacitors with controlled electrical capacity in the pF–nF range printed by laser-induced forward transfer (LIFT)

Micrometric-sized pixels of hybrid organic–inorganic thin films (Ag/parylene-C) have been printed by laser-induced forward transfer (LIFT) on flexible, cost-efficient substrates. Micrometric capacitors have been fabricated by laser printing such pixels together with silver nanoparticles (AgNP) paste. The AgNP paste has been deposited in the shape of square pads, acting as bottom electrode. This combination is suitable to be used in microelectronic circuits, as the electrical components exhibit controllable capacity in the pF–nF range. Electrical characterizations of the printed pixels demonstrate that the capacitors are fully operative and stable over time.     

Current multiplication in MIS structures

In this paper, the current multiplication mechanism in MIS structures is studied theoretically by employing a parameter, φ, which indicates the degree of inversion of the MIS system. Current expressions for majority carriers as well as minority carriers are derived in terms of this parameter. V_ao, the voltage drop across the sandwiched insulator is also calculated by solving Poisson's equation for the system, in terms of this parameter. The calculated V_ao is then used to compute the multiplication factor for the system. Because of the use of this parameter, a clear view of the physical process of the multiplication mechanism is obtained from the analysis.The following results are obtained for MIS structures through this study: (1) For MIS with a thin insulator (γ 50 Å), V_ao is negligibly small before the MIS is in inversion and increases rapidly after the MIS is in inversion. (2) For MIS with a thin insulator, φ_(inv) is independent of the applied voltage. (3) An MIS with a thicker insulator has a larger current multiplication than that of an MIS with a thinner insulator. (4) An MIS with a lower φ_Bn, the electron barrier height, has a larger current multiplication.     

Generation of surface electron states with a silicon–ultrathin-oxide interface under the field-induced damage of metal–oxide–semiconductor structures

The high-frequency capacitance–voltage characteristics of metal–oxide–semiconductor structures on n-Si substrates with an oxide thickness of 39 Å are studied upon being subjected to damage by field stress. It is shown that the action of a high, but pre-breakdown electric field on an ultrathin insulating layer brings about the formation of a large number of additional localized interface electron states with an energy level arranged at 0.14 eV below the conduction band of silicon. It is found that, as the field stress is increased, the recharging of newly formed centers provides the accumulation of excess charge up to 8 × 10¹² cm^–2 at the silicon–oxide interface. The lifetime of localized centers created under field stress is two days, after which the dependences of the charge localized at the semiconductor–insulator interface on the voltage at the gate after and before field stress are practically the same.     

Modeling the equivalent oxide thickness of Surrounding Gate SOI devices with high-κ insulators

In this work, the behavior of the gate insulator capacitance of different Surrounding Gate SOI devices with square and circular cross-sections has been studied. It is shown that the equivalent oxide thickness used for planar devices is not valid for devices with bidimensional confinement. For this kind of devices, new expressions for the gate insulator capacitance and equivalent oxide thickness are obtained using an approximate model of metal–insulator–metal capacitors. These expressions depend not only on the dielectric constant but also on the geometry of the device under consideration since for non-planar devices geometry plays an important role in the behavior of the C–V characteristics. The new expressions are validated by numerical simulations of these Multiple-Gate (MuG) devices that take into account quantum effects.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

MOS栅氧的界面特性和辐照特性研究

通过交流电导法,对经过不同时间N₂O快速热处理(RTP)的MOS电容进行界面特性和辐照特性研究。通过电导电压曲线,分析N₂O RTP对Si-SiO₂界面陷阱电荷和氧化物陷阱电荷造成的影响。结论表明,MOS电容的Si-SiO₂界面陷阱密度随N₂O快速热处理时间先增加再降低;零偏压总剂量辐照使氧化层陷阱电荷显著增加,而Si-SiO₂界面陷阱电荷轻微减少。     

Modified Interface Properties of Au/<Emphasis Type="Italic">n</Emphasis>-type GaN Schottky Junction with a High-<Emphasis Type="Italic">k</Emphasis> Ba<Subscript>0.6</Subscript>Sr<Subscript>0.4</Subscript>TiO<Subscript>3</Subscript> Insulating Layer

The interface properties of a Au/n-GaN Schottky junction (SJ) were modified by placing a high-k barium strontium titanate (Ba_0.6Sr_0.4TiO₃) insulating layer between the Au and n-GaN semiconductor. The surface morphology, chemical composition, and electrical properties of Au/Ba_0.6Sr_0.4TiO₃ (BST)/n-GaN metal/insulator/semiconductor (MIS) junctions were explored by atomic force microscopy, energy-dispersive x-ray spectroscopy, current–voltage (I–V) and capacitance–voltage (C–V) techniques. The electrical results of the MIS junction are correlated with the SJ and discussed further. The MIS junction exhibited an exquisite rectifying nature compared to the SJ. An average barrier height (BH) and ideality factors were extracted to be 0.77 eV, 1.62 eV and 0.92 eV, 1.95 for the SJ and MIS junction, respectively. The barrier was raised by 150 meV for the MIS junction compared to the MS junction, implying that the BH was effectively altered by the BST insulating layer. The BH values extracted by I–V, Cheung’s and Norde functions were nearly equal to one another, indicating that the techniques applied here were dependable and suitable. The frequency-dependent properties of the SJ and MIS junction were explored and discussed. It was found that the interface state density of the MIS junction was smaller than the SJ. This implies that the BST layer plays an imperative role in the decreased N_SS. Poole–Frenkel emission was the prevailed current conduction mechanism in the reverse-bias of both the SJ and MIS junction.     

Reliability issues of double gate dielectric stacks based on hafnium dioxide (HfO2) layers for non-volatile semiconductor memory (NVSM) applications

In this study, we present selected reliability issues of double gate dielectric stacks for non-volatile semiconductor memory (NVSM) applications. Fabricated gate structures were consisted of PECVD silicon oxynitride layer (SiO_xN_y) as the pedestal layer and hafnium dioxide layer (HfO₂) as the top gate dielectric. In the course of this work, obtained MIS structures were investigated by means of current–voltage characteristics, as well as applying dc stresses in constant current (CCS) and voltage (CVS) mode. Presented results have shown that the application of ultra-thin PECVD silicon oxynitride layer results in significant increase of breakdown voltage value in comparison to MIS structure with only hafnia as the gate dielectric. Moreover, due to the high temperature annealing of deposited SiO_xN_y layers, MIS device demonstrates much lower leakage currents, as well as higher breakdown voltage values in comparison to device with ‘as-deposited’ SiO_xN_y bottom layer. The results also proved larger immunity to dc stresses and better retention characteristics of MIS devices with ‘annealed’ oxynitride, in comparison to ‘as-deposited’ pedestal layer.     

Specific features of the capacitance–voltage characteristics of a Cu–SiO<Subscript>2</Subscript>–<Emphasis Type="Italic">p</Emphasis>-InSb MIS structure

The capacitance–voltage and conductance–voltage characteristics of InSb-based MIS structures are measured at different probe signal frequencies with the aim of studying the influence exerted by the technological-synthesis conditions on the capacitive properties of these structures. The influence of positive charge built into the insulator on the sample characteristics is discussed. This influence manifests itself as a sharp capacitance “switch” upon changing the polarity of a low-field (E < 10⁶ V/cm) external signal.     

Electrical properties of ZnO Nano-particles embedded in polyimide

The ZnO nano-particles were made in the polyimide dielectric matrix by using the chemical reaction between the zinc metal film and polyamic acid. The concentration of the ZnO particle is about 1.5×10¹² cm⁻², with average size below 10 nm, and its shapes are almost spherical. Then, the polyimide layer is a stable dielectric material with a dielectric constant of 2.9. To investigate the electrical properties of ZnO particles in the polyimide insulator film, we fabricated a metal-insulator-semiconductor (MIS) structure and measured capacitance-voltage (C-V) with temperature modulation. At room temperature, C-V hysteresis with a voltage gap of 2.8 V appeared in the MIS structure using SiO₂/Si substrate. As the measuring temperature decreased, the C-V curves were shifted slightly to the accumulation region with gate bias. It was considered that the electrical charging may occur dominantly in nanoparticles, having only a few defects at the interface of the polyimide/SiO₂ and the polyimide/ZnO.