GaAs MOSFETs fabrication with a selective liquid phase oxidizedgate

The N-channel depletion-mode GaAs MOSFETs with a liquid phase chemical enhanced selective gate oxide grown at low temperature are demonstrated. The proposed selective oxidation method makes the fabrication process of GaAs MOSFETs more reliable and self side-wall passivation possible. The fabricated GaAs MOSFETs exhibit current-voltage characteristics with complete pinch-off and saturation characteristics. The 2 μm gate-length MOSFETs with a gate oxide thickness of 35 nm show transconductance larger than 80 mS/mm and maximum drain current density of 380 mA/mm. In addition, microwave characteristics with f_T of 1.8 GHz and f_max of 5.2 GHz have been achieved from the 3 μm×60 μm GaAs MOSFETs     

Tunneling through ultrathin GaAs n++-p++-n++ barrier grown by molecular layer epitaxy

The I-V characteristics of ultrathin GaAs n⁺⁺-p⁺⁺ -n⁺⁺ barrier structures with a 45 Å thick p⁺⁺ layer grown by molecular layer epitaxy (MLE) have been measured at room temperature and 77 K. The tunneling probability for this structure has been calculated as a function of effective tunneling width. It was found that good agreement between experiment and calculation is obtained when the effective tunneling width is assumed to be 75 Å, which is much smaller than the depletion width about 190 Å measured by C-V method. This fact indicates that the depletion width approximation cannot be used to measure the exact tunneling width for ultrathin barrier devices     

On the behaviour of buried oxygen implanted layers in highly doped GaAs

Highly doped GaAs substrate material (doping level 10¹⁸ cm⁻³) has been implanted with 350 keV O⁺ ions with doses of 10¹⁴ – 10¹⁶ cm⁻² to produce high resistivity layers which are stable at high temperatures. LPE growth of flat GaAs epilayers onto the implanted wafers was achieved up to doses of about 1 × 10¹⁵ O⁺/cm² and 5 × 10¹⁵O⁺/cm² for RT and 200°C implants, respectively. N-o-n and p-o-n structures (o: oxygen implanted) were fabricated in which breakdown voltages of up to 15 V were obtained. Examples for application of this isolation technique are shown.     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

Material and ultrafast optoelectronic properties offurnace-annealed arsenic-ion-implanted GaAs

Structural, electrical, and ultrafast optical properties of furnace-annealed arsenic-ion-implanted GaAs (GaAs:As⁺) has been investigated for its applications in ultrafast optoelectronics. From these studies, we determine that GaAs substrates implanted with 200-keV arsenic ions at 10¹⁰ ions/cm² and furnace-annealed at 500°C-600°C would have recovered its crystallinity, be highly resistive, and exhibit picosecond photo-excited carrier lifetimes. The duration of the electrical pulses generated by photoconductive switches (PCSs) fabricated on the optimized material was ≈4 ps. The risetime (10%-90%) and l/e falltime were, respectively, ≈2 and 3 ps. These results were measurement-system limited. We estimated the actual response to be ≈2 ps, consistent with a photo-excited carrier lifetime of ≈1.8 ps. The peak responsivity was ⩾4×10^-3 A/W. The dark current for the GaAs:As⁺ PCS biased at 40 V was as low as 5 nA. The breakdown field was higher than 150 kV/cm. These characteristics are comparable to those of state-of-the-art photoconductors such as LT-GaAs     

GaAs/AlGaAs heterojunction Pnp bipolar transistors grownon (100) Si by molecular beam epitaxy

GaAs/AlGaAs Pnp heterojunction bipolar transistors (HBTs) were fabricated and tested on (100) Si substrates for the first time. A common-emitter current gain of β=8 was measured for the typical devices with an emitter area of 50×50 μm² at a collector current density of 1×10⁴ A/cm² with no output negative differential resistance up to 280 mA, highest current used. A very high base-collector breakdown voltage of 10 V was obtained. Comparing the similar structures grown on GaAs substrates, the measured characteristics clearly demonstrate that device grade hole injection can be obtained in GaAs on Si epitaxial layers despite the presence of dislocations     

Electrical characteristics of MOSFETs using low-pressurechemical-vapor-deposited oxide

The electrical characteristics of MOSFETs and MOS capacitors utilizing thin (80-230 Å) low-pressure chemical-vapor-deposited (LPCVD) oxide films deposited at 12 Å/min are presented. MOSFETs using CVD oxides show good electrical characteristics with 70-90% of the surface mobility of conventional MOSFETs. The CVD oxides exhibit the same low leakage current and high breakdown fields as the thermal oxides, and significantly lower trapping and trap generation rates than thermally grown oxides. Interface state densities of ⩽3×10¹⁰ cm^-2 eV^-1 are obtained from CVD devices by using a short annealing in oxygen ambient following the deposition. These results indicate that these LPCVD oxide films may be promising dielectrics for MOS device application     

Lateral n-channel inversion mode 4H-SiC MOSFETs

Advances in MOS devices on silicon carbide (SiC) have been greatly hampered by the low inversion layer mobilities. In this paper, the electrical characteristics of lateral n-channel MOSFETs fabricated on 4H-SiC are reported for the first time. Inversion layer electron mobilities of 165 cm²/V·s in 4H-SiC MOSFETs were measured at room temperature. These MOSFETs were fabricated using a low temperature deposited oxide, with subsequent oxidation anneal, as the gate dielectric     

High-quality CMOS in thin (100 nm) silicon on sapphire

Electrical characteristics of enhancement-mode n-channel and p-channel MOSFETs in 100-nm-thick silicon-on-sapphire (SOS) are reported. Channel mobilities (linear operation) of 500 and 200 cm² /V-s, respectively, have been measured in double solid-phase epitaxially (DSPE) improved material. Deep trap levels associated with the Si-sapphire interface were measured in concentrations as low as 1×10¹¹ cm^-2. These results indicate that DSPE-improved SOS films thinned to 100 nm are suitable for application to high-performance down-scaled CMOS circuitry     

InAs/AlSb double-barrier structure with large peak-to-valleycurrent ratio: a candidate for high-frequency microwave devices

Negative differential resistance (NDR) in InAs/AlSb/InAs/AlSb/InAs double-barrier structures with peak-to-valley current (PVC) ratios as large as 11 at room temperature and 28 at 77 K is reported. This is a large improvement over previous results for these materials and is also considerably better than those obtained for the extensively studied GaAs/AlGaAs material system. The peak current density was also improved by reducing the barrier thickness, and values exceeding 10⁵ A/cm² have been observed. These results suggest that InAs/AlSb structures are interesting alternatives to conventional GaAs/AlGaAs structures in high-frequency devices. NDR in a InAs/AlSb superlattice double-barrier structure with a lower PVC ratio than in the solid barrier case has also been observed. This result indicates that valley current contributions arising from X-point tunneling are negligible in these structures, consistent with the large band offset     

Subquarter-micrometer gate-length p-channel and n-channel MOSFETswith extremely shallow source-drain junctions

The fabrication of p-channel and n-channel MOSFETs with sub-quarter-micrometer n⁺ polysilicon gates, have been fabricated using extremely shallow source-drain (S-D) junctions, is reported p⁺-n junctions as shallow as 80 nm have been fabricated using preamorphization low-energy BF₂ ion implantation and rapid thermal annealing, and 80-nm n⁺-p junctions have been fabricated using low-energy arsenic ion implantation and rapid thermal annealing. n-channel MOSFETs with 80-mm S-D junctions and 0.16-μm gate lengths have been fabricated, and a maximum transconductance of 400 mS/mm has been obtained. 51-stage n-channel enhancement-mode/enhancement-mode (E/E) ring oscillators and p-channel E/E ring oscillators with extremely shallow S-D junctions have also been obtained     

⟨110⟩-oriented GaAs MESFETs

GaAs metal semiconductor field-effect transistors (MESFETs) have been successfully fabricated on molecular-beam epitaxial (MBE) films grown on the off-axis (110) GaAs substrate. The (110) substrates were tilted 6° toward the (111) Ga face in order to produce device quality two-dimensional MBE growth. Following the growth of a 0.4-μm undoped GaAs buffer, a 0.18-μm GaAs channel with a doping density of 3.4×10¹⁷ cm^-3 and a 0.12-μm contact layer with a doping density of 2×10¹⁸ cm^-3, both doped with Si, were grown. MESFET devices fabricated on this material show very low-gate leakage current, low output conductance, and an extrinsic transconductance of 200 mS/mm. A unity-current-gain cutoff frequency of 23 GHz and a maximum frequency of oscillation of 56 GHz have been achieved. These (110) GaAs MESFETs have demonstrated their potential for high-speed digital circuits as well as microwave power FET applications     

Metamorphic InP/InGaAs heterojunction bipolar transistors on GaAssubstrate: DC and microwave performances

High-performance InP/In_0.53Ga_0.47As metamorphic heterojunction bipolar transistors (MHBTs) on GaAs substrate have been fabricated using In_xGa_1-xP strain relief buffer layer grown by solid-source molecular beam epitaxy (SSMBE). The MHBTs exhibited a dc current gain over 100, a unity current gain cutoff frequency (f_T) of 48 GHz and a maximum oscillation frequency (f_MAX) of 42 GHz with low junction leakage current and high breakdown voltages. It has also been shown that the MHBTs have achieved a minimum noise figure of 2 dB at 2 GHz (devices with 5×5 μm ² emitter) and a maximum output power of 18 dBm at 2.5 GHz (devices with 5×20 μm² emitter), which are comparable to the values reported on the lattice-matched HBTs (LHBTs). The dc and microwave characteristics show the great potential of the InP/InGaAs MHBTs on GaAs substrate for high-frequency and high-speed applications     

An In0.15Ga0.85As/GaAs pseudomorphic single quantum well HEMT

This letter describes high electron mobility transistors (HEMT's) utilizing a conducting channel which is a single In0.15Ga0.85AS quantum well grown pseudomorphically on a GaAs substrate. A Hall mobility of 40 000 cm²/V.s has been observed at 77 K. Shubnikov-de Haas oscillations have been observed at 4.2 K which verify the existence of a two-dimensional electron gas at the In0.15Ga0.85As/GaAs interface. HEMT's fabricated with 2-µm gate lengths show an extrinsic transconductance of 90 and 140 mS/mm at 300 and 77 K, respectively-significantly larger than that previously reported for strained-layer superlattice InxGa1-xAs structures which are nonpseudomorphic to GaAs substrates. HEMT's with 1-µm gate lengths have been fabricated, which show an extrinsic transconductance of 175 mS/mm at 300 K which is higher than previously reported values for both strained and unstrained InxGa1-xAs FET's. The absence of AlxGa1-xAs in these structures has eliminated both the persistent photoconductivity effect and drain current collapse at 77 K.     

A semi-empirical model for the field-effect mobility ofhydrogenated polycrystalline-silicon MOSFETs

The quantitative relationship between field-effect mobility (μ _FE) and grain-boundary trap-state density (N_t ) in hydrogenated polycrystalline-silicon (poly-Si) MOSFETs is investigated. The focus is on the field-effect mobility in MOSFETs with N_t 1×10² cm^-2. It is found that reducing N_t to as low as 5×10¹¹ cm^-2 has a great impact on μ_FE. MOSFETs with the N_t of 4.2×10¹¹ cm^-2 show an electron mobility of 185 cm²/V-s, despite a mean grain size of 0.5 μm. The three principal factors that determine μ_FE, namely, the low-field mobility, the mobility degradation factor, and the trap-state density N_t are clarified     

New aspects and mechanism of kink effect in static back-gatetransconductance characteristics in fully-depleted SOI MOSFETs onhigh-dose SIMOX wafers

An extraordinary kink phenomenon in static back-gate transconductance characteristics of fully-depleted SOI MOSFETs has been experimentally investigated and characterized for the first time. This kink phenomenon has been observed in both NMOS and PMOS on high-dose SIMOX wafers under steady-state conditions at room temperature. It was also found that the back-gate characteristics for both NMOS and PMOS show anomalous shift phenomenon in drain current-back gate voltage (I _D-V_G2) curve at the back-gate voltage corresponding to the kink phenomenon. This kink phenomenon has been attributed to the presence of energetically-localized trap states at SOI/BOX interface. In order to clarify the energy level of the trap states at SOI/BOX interface corresponding to the kink, we have developed a new formula of surface potential in thin-film SOI MOS devices, in which the potential drop across semiconductor-substrate is taken into account. By using this new formula, me have demonstrated that high-dose SIMOX wafers have donor-like electron trap states at ~0.33 eV above the Si midgap with the density of ~N6.0~10¹² cm^-2 eV ^-1 and donor-like hole trap states at ~0.35 eV below the Si midgap with density of ~1.5×10¹² cm^-2 eV^-1 at SOI/BOX interface     

Quantum-well Hall devices in Si-delta-dopedAl0.25Ga0.75As/GaAs and pseudomorphic Al0.25Ga0.75As/In0.25Ga0.75As/GaAsheterostructures grown by LP-MOCVD: performance comparisons

Characterized herein are quantum-well Hall devices in Si-delta-doped Al_0.25Ga_0.75As/GaAs and pseudomorphic Al_0.25Ga_0.75As/In_0.25Ga _0.75As/GaAs heterostructures, grown by low-pressure metal organic chemical vapor deposition method. The Si-delta-doping technique has been applied to quantum-well Hall devices for the first time. As a result high electron mobilities of 8100 cm^-2/V·s with a sheet electron density of 1.5×10¹² cm^-2 in Al_0.25Ga_0.75As/In_0.25Ga_0.75 As/GaAs structure and of 6000 cm^-2/V·s with the sheet electron density of 1.2×10¹² cm^-2 in Al_0.25Ga_0.75As/GaAs structure have been achieved at room temperature, respectively. From Hall devices in Al_0.25Ga_0.75As/In_0.25Ga_0.75 As structure, the product sensitivity of 420 V/AT with temperature coefficient of -0.015 %/K has been obtained. This temperature characteristic is one of the best result reported. Additionally, a high signal-to-noise ratio corresponding to the minimum detectable magnetic field of 45 nT at 1 kHz and 75 nT at 100 Hz has been attained. These resolutions are among the best reported results     

Fabrication of 200-GHz fmax resonant-tunnelingdiodes for integration circuit and microwave applications

Room-temperature current densities of 1.3×10⁵ A/cm² and peak-to-valley ratios of 2.5 have been achieved for resonant tunneling diodes (RTDs) in the GaAs/AlAs material system. The devices were fabricated in a microwave-compatible process using topside contacts and a semi-insulating substrate to allow device integration. Proton implantation creates a nonconducting surface compatible with high-frequency coplanar transmission lines and other passive microwave structures     

Refractory metal silicon device technology

Films 2000–5000 Å thick of Mo or W deposited over thin films of thermally grown SiO₂ are shown to be effective high temperature diffusion masks against both phosphorous and boron. These metal films may be precisely patterned and their diffusion masking properties can be used to define the source and drain regions of MOSFETs. In this manner, self-registered MOSFETs can be fabricated with a portion of the diffusion masking metal film acting as the gate electrode. Using P or B doped deposited glasses as diffusion sources, n or p channel enhancement mode MOSFETs were made by diffusion through the exposed thin SiO₂ film into p and n type Si to form source and drain junctions. Contact was subsequently made by etching holes through the oxide layers to the source and drain regions and to the refractory metal gate electrode buried within the oxide layers. These devices exhibit channel mobilities between 200 and 300 cm²/V-sec at gate voltages about 10 V above threshold. The stability of MOS structures processed in a similar manner has been measured. After being stressed at ±6 × 10⁵ V/cm and 250°C for 15 hr, these devices exhibited shifts in their C---V characteristics less than 200 mV.     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made