一种新型的集成电路金属连线温度分析解析模型

研究了金属连线上的焦耳热对连线温度的影响,进而提出了一种新型的集成电路多层金属连线上的温度模拟器(LTem).该模拟器采用一种相对简单的热学解析模型,详细考虑了通孔效应以及边缘效应对温度分布的影响.模拟结果表明,考虑了通孔效应以及边缘效应之后,金属连线上的温度分布情况有了较大程度上的降低,LTem可以得到更贴近实际情况的金属连线温度分布情况.     

通孔对金属连线温度分布的影响

详细讨论了考虑通孔自热的金属连线温度分布模型,并通过该模型,计算了不同通孔直径和高度情况下,单一及并行金属连线的温度分布。计算结果表明,通孔直径和通孔高度及并行金属连线间的热耦合对金属连线温度分布有重大的影响。     

ULSI中金属互连系统上的热点分析

针对金属互连系统上的热点将对集成电路芯片的性能和可靠性产生重大的影响,详细讨论了ULSI金属互连系统上的热点位置和温度分布模型,并通过该模型比较了不同通孔直径和高度情况下,金属互连系统上的热点位置和温度的差别。结果表明,通孔直径和高度对金属互连系统上的热点有重大的影响。     

考虑温度分布效应的RLC互连延时分析

基于等效Elmore延时模型和分段分布参数思想提出了一种RLC互连延时解析模型,该模型同时考虑了互连线温度分布效应和电感效应对延时的影响,更加贴近实际情况,在实际应用中具有重要意义. 仿真结果表明,对于简单的RLC互连树形结构而言,所提模型的延时误差在10%以内,且仿真效率高.     

考虑温度分布效应的RLC互连延时分析

基于等效Elmore延时模型和分段分布参数思想提出了一种RLC互连延时解析模型,该模型同时考虑了瓦连线温度分布效应和电感效应对延时的影响,更加贴近实际情况,在实际应用中具有重要意义.仿真结果表明,对于简单的RLC互连树形结构而言,所提模型的延时误差在10%以内,且仿真效率高.     

低阻硅CMOS工艺片上互连线模型

提出了一种新的互补金属氧化物半导体(CMOS)工艺片上的互连线模型,模型在考虑互连线金属导体高频效应和衬底效应的基础上,引入了一个电容来表征金属导体通过氧化层在低阻硅衬底中引起的容性耦合特性.建立的互连线模型通过0.18 μm CMOS工艺上制作的互连线测试数据验证,频率精度可至50 GHz.     

用模拟退火算法实现集成电路热布局优化

介绍了一种综合考虑集成电路电学性能指标以及热效应影响的布局优化方法 .在保证传统设计目标 (如芯片面积、连线长度、延迟等 )不被恶化的基础上 ,通过降低或消除芯片上的热点来优化集成电路芯片的温度分布情况 ,进而优化整个电路性能 .并将改进的模拟退火算法应用于集成电路的热布局优化 ,模拟结果表明该方法与传统布局方法相比在保持了较好的延迟与连线长度等设计目标的同时 ,很好地改善了芯片表面的热分配情况     

用模拟退火算法实现集成电路热布局优化

介绍了一种综合考虑集成电路电学性能指标以及热效应影响的布局优化方法.在保证传统设计目标(如芯片面积、连线长度、延迟等)不被恶化的基础上,通过降低或消除芯片上的热点来优化集成电路芯片的温度分布情况,进而优化整个电路性能.并将改进的模拟退火算法应用于集成电路的热布局优化,模拟结果表明该方法与传统布局方法相比在保持了较好的延迟与连线长度等设计目标的同时,很好地改善了芯片表面的热分配情况.     

Kirchhoff近似的研究

用数值方法讨论了应用Ｋｉｒｃｈｈｌｆｆ近似计算粗糙面电磁散射时，考虑边缘效应与不考虑边缘效应，计算Ｆｒｅｓｎｅｌ反射系数时用全局人射角与用局地入射角，考虑与不考虑遮挡效应，七不考虑二阶相互作用对计算结果的影响。     

ULSI中铜互连线通孔电热性能的数值模拟

利用三维有限元模型对Cu互连线通孔进行了电流密度、温度和温度梯度的分布进行了模拟,比较了具有不同阻挡层材料的通孔内的电流密度、温度和温度梯度的分布.对于同一阻挡层材料,进行了不同通孔倾斜角的模拟.模拟结果指出,通过优化通孔倾斜角和优选阻挡层材料可有效地改善通孔内的电流密度和温度的分布,提高ULSI通孔互连的可靠性,这对通孔的设计提供了有益的参考.     

超大规模集成电路互连系统的布线构造对散热的影响

应用一个三层互连布线结构研究了诸多因素尤其是布线的几何构造对互连系统散热问题的影响,并对多种不同金属与介质相结合的互连布线的散热情况进行了详细模拟.研究表明互连线上焦耳热的主要散热途径为金属层内的金属线和介质层中热阻相对小的路径.因此互连系统的几何布线对系统散热具有重要影响.在相同条件下,铝布线系统的温升约为铜布线的ρAl/ρCu倍.此外,模拟了0.13μm工艺互连结构中连接功能块区域的信号线上的温升情况,探讨了几种用于改善热问题的散热金属条对互连布线的导热和附加电容的影响.     

Evaluation of CVD/PVD multilayered seed for electrochemicaldeposition of Cu-damascene interconnects

Multilayered seed for electrochemical deposition (ECD) of Cu was investigated to develop narrow-pitched, dual-damascene Cu interconnects that will be required for future ULSI devices. The seed was obtained by the physical vapor deposition (PVD) of a Cu film followed by the chemical vapor deposition (CVD) of a Cu film. The seed of the thinner CVD-Cu element and the thicker PVD-Cu element demonstrated better filling characteristics in high-aspect ratio vias. Good current-voltage characteristics were demonstrated using the multilayered seed technique with Cu dual-damascene interconnects (0.28 μm minimum via size) resulting in a via resistance about 0.7 Ω. In addition, ring-oscillator circuits were fabricated by integrating the double-layered interconnects with a transistor having a 0.18 μm gate width. The propagation delay per inverter, which had an interconnect with 10⁴ vias, was about 6 ns. We successfully fabricated multilevel Cu-damascene interconnects, which are available for future high-speed devices using this multilayered seed technique     

深亚微米多层互连的温度分布特性分析

本文从热扩散方程出发,推导了简单互连的温度分布解析表达式,采用65nm工艺参数,详细讨论了热扩散长度和介质层厚度对互连温度分布的影响;进一步给出了复杂多层互连的温度分布解析表达式并用于其特性模拟,结果显示全局互连的温升远大于半全局互连和局部互连的温升。     

ULSI多层Cu布线CMP中磨料的研究

超大规模集成电路多层Cu布线平坦化中,抛光磨料是CMP系统的重要组成部分,是决定抛光速率、抛光表面状态和平坦化能力的重要影响因素.分析研究了在CMP中磨料的作用和影响,指出碱性的纳米级SiO2水溶胶是ULSI多层Cu布线CMP的理想磨料.并进一步通过对多层Cu布线CMP硅溶胶磨料的优化研究,指出采用小粒径、低粒径分散度、高质量分数的SiO2水溶胶磨料,可有效地解决平整度差、塌边、碟形坑、表面粗糙度差等问题,获得了良好的抛光效果.     

Analytical thermal model for multilevel VLSI interconnectsincorporating via effect

The authors present compact analytical thermal models for estimating the temperature rise of multilevel VLSI interconnect lines incorporating via effect. The impact of vias has been modeled using (1) a characteristic thermal length and (2) an effective thermal conductivity of ILD (interlayer dielectric), k_ILD,eff, with k _ILD,_eff=k_ILDη/, where η is a physical correction factor, with 0<η<1. Both the spatial temperature profile along the metal lines and their average temperature rise can be easily obtained using these models. The predicted temperature profiles are shown to be in excellent agreement with the three-dimensional (3-D) finite element thermal simulation results. The model is then applied to estimate the temperature rise of densely packed multilevel interconnects. It is shown that for multilevel interconnect arrays, via density along the lines can significantly affect the temperature rise of such interconnect structures     

Comparative study of novel barrier layers in ULSI copper interconnects

As ULSI dimensions shrink, conventional Ta/TaN barriers will not meet the future demands for ULSI interconnects, i.e. thin conformal layer without overhangs. In this paper, we have compared the material properties of TaN/Ta barriers with Ta only and W based barriers by means of XRD, AFM, Stress and SEM imaging. We found that using a conformal CVD W based barriers has great potential for future ULSI interconnects. It grain size and tensile stress improve resistance to both electromigration and stress migration, extending conductor lifetime.     

Influence of air gaps on the thermal–electrical–mechanical behavior of a copper metallization

Shrinking the IC dimensions the dielectric insulation between metal interconnects has become one of the major limits on increasing circuit speed. A lot of possible new low-k materials failed to meet specifications: too leaky, too soft, too unstable, and too expensive. Due to this air gaps beside the metallization are one solution. The reliability of ULSI multilevel copper metallizations under electro- and stress migration stress test conditions is investigated here with finite element analysis. A determination of the electrical and mechanical stress in a 3D copper metallization model based on the 45 nm technology node is carried out and the impact of a variation of the applied current density as well as geometrical parameters on the thermal–electrical and mechanical behavior is investigated. For a determination of the reliability the mass flux and mass flux divergence are separately calculated by a user routine. The influence of air gaps on single via structures and structures with a chain of four vias on the thermal–electrical–mechanical behavior is determined.     

2001 needs for multi-level interconnect technology

Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects. It is shown that ad hoc executions of programs to calculate interconnect parameters for VLSI/ULSI design and analysis are too time-consuming to be practical. The tool used in this study to model a hypothetical interconnect system was Hewlett Packard's HTVE (HP Interconnect Value Extractor)     

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.     

0.18μm Low—k SiOF Integration and Reliability

The requirement of reduced RC delay and cross-talk for multilevel interconnect ULSI applications has enthusiastically driven process development for seeking suitable low dielectric constant materials with sufficient k value.The replacement of HDP FSG(k-3.5-3.6)with conventional SiO2 as a manufacturable intermetal dielectric layer(IMD) has achieved 0.18μm ULSI interconnect technology.The electrical test result,via resislance as well as multilevel CMOS transistor characteristics (such as plasma damage,device degradation,hot carrier,etc.)are basically compatible to those conventional oxide as IMD.Assessment of metal line-to-line capacitance reduction using comb capacitors yields values of reduction range 10%-14% comparing FSG to convention oxide.The effectiveness of low-k FSG in circuit performance is also demonstrated.Comparisons of ring-oscillator speed performance for metal runners with various width and space show speed improvement approximately 10% for the FSG.Impact of FSG on reliability is evaluated and results show manufacturing compatibility to conventional SiO2.